prev_cmp_serial_uart_top.tan.qmsg

来自「FPGA Cycloneii 系列的」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "ITDB_TSU_RESULT" "uart_top:inst\|detector:inst9\|state RXD clk 4.365 ns register " "Info: tsu for register \"uart_top:inst\|detector:inst9\|state\" (data pin = \"RXD\", clock pin = \"clk\") is 4.365 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.266 ns + Longest pin register " "Info: + Longest pin to register delay is 7.266 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.843 ns) 0.843 ns RXD 1 PIN PIN_F14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = PIN_F14; Fanout = 3; PIN Node = 'RXD'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { RXD } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 216 56 72 384 "RXD" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.782 ns) + CELL(0.545 ns) 7.170 ns uart_top:inst\|detector:inst9\|state~162 2 COMB LCCOMB_X34_Y15_N0 1 " "Info: 2: + IC(5.782 ns) + CELL(0.545 ns) = 7.170 ns; Loc. = LCCOMB_X34_Y15_N0; Fanout = 1; COMB Node = 'uart_top:inst\|detector:inst9\|state~162'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.327 ns" { RXD uart_top:inst|detector:inst9|state~162 } "NODE_NAME" } } { "detector.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/detector.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 7.266 ns uart_top:inst\|detector:inst9\|state 3 REG LCFF_X34_Y15_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 7.266 ns; Loc. = LCFF_X34_Y15_N1; Fanout = 2; REG Node = 'uart_top:inst\|detector:inst9\|state'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { uart_top:inst|detector:inst9|state~162 uart_top:inst|detector:inst9|state } "NODE_NAME" } } { "detector.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/detector.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.484 ns ( 20.42 % ) " "Info: Total cell delay = 1.484 ns ( 20.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.782 ns ( 79.58 % ) " "Info: Total interconnect delay = 5.782 ns ( 79.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.266 ns" { RXD uart_top:inst|detector:inst9|state~162 uart_top:inst|detector:inst9|state } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.266 ns" { RXD RXD~combout uart_top:inst|detector:inst9|state~162 uart_top:inst|detector:inst9|state } { 0.000ns 0.000ns 5.782ns 0.000ns } { 0.000ns 0.843ns 0.545ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "detector.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/detector.v" 38 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.863 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.863 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.602 ns) 2.863 ns uart_top:inst\|detector:inst9\|state 3 REG LCFF_X34_Y15_N1 2 " "Info: 3: + IC(0.997 ns) + CELL(0.602 ns) = 2.863 ns; Loc. = LCFF_X34_Y15_N1; Fanout = 2; REG Node = 'uart_top:inst\|detector:inst9\|state'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.599 ns" { clk~clkctrl uart_top:inst|detector:inst9|state } "NODE_NAME" } } { "detector.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/detector.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.86 % ) " "Info: Total cell delay = 1.628 ns ( 56.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.235 ns ( 43.14 % ) " "Info: Total interconnect delay = 1.235 ns ( 43.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.863 ns" { clk clk~clkctrl uart_top:inst|detector:inst9|state } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.863 ns" { clk clk~combout clk~clkctrl uart_top:inst|detector:inst9|state } { 0.000ns 0.000ns 0.238ns 0.997ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.266 ns" { RXD uart_top:inst|detector:inst9|state~162 uart_top:inst|detector:inst9|state } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.266 ns" { RXD RXD~combout uart_top:inst|detector:inst9|state~162 uart_top:inst|detector:inst9|state } { 0.000ns 0.000ns 5.782ns 0.000ns } { 0.000ns 0.843ns 0.545ns 0.096ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.863 ns" { clk clk~clkctrl uart_top:inst|detector:inst9|state } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.863 ns" { clk clk~combout clk~clkctrl uart_top:inst|detector:inst9|state } { 0.000ns 0.000ns 0.238ns 0.997ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk data_led_4\[6\] instruc2main:inst6\|FIFO1_time\[0\] 18.675 ns register " "Info: tco from clock \"clk\" to destination pin \"data_led_4\[6\]\" through register \"instruc2main:inst6\|FIFO1_time\[0\]\" is 18.675 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.199 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.199 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.656 ns) + CELL(0.879 ns) 3.561 ns uart_top:inst\|uart_core:inst\|recv 2 REG LCFF_X27_Y15_N31 19 " "Info: 2: + IC(1.656 ns) + CELL(0.879 ns) = 3.561 ns; Loc. = LCFF_X27_Y15_N31; Fanout = 19; REG Node = 'uart_top:inst\|uart_core:inst\|recv'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { clk uart_top:inst|uart_core:inst|recv } "NODE_NAME" } } { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.869 ns) + CELL(0.879 ns) 5.309 ns get:inst5\|dataout3\[5\] 3 REG LCFF_X25_Y15_N17 1 " "Info: 3: + IC(0.869 ns) + CELL(0.879 ns) = 5.309 ns; Loc. = LCFF_X25_Y15_N17; Fanout = 1; REG Node = 'get:inst5\|dataout3\[5\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.748 ns" { uart_top:inst|uart_core:inst|recv get:inst5|dataout3[5] } "NODE_NAME" } } { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.455 ns) 6.137 ns instruc2main:inst6\|FIFO1_amp\[6\]~140 4 COMB LCCOMB_X25_Y15_N14 1 " "Info: 4: + IC(0.373 ns) + CELL(0.455 ns) = 6.137 ns; Loc. = LCCOMB_X25_Y15_N14; Fanout = 1; COMB Node = 'instruc2main:inst6\|FIFO1_amp\[6\]~140'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.828 ns" { get:inst5|dataout3[5] instruc2main:inst6|FIFO1_amp[6]~140 } "NODE_NAME" } } { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.504 ns) + CELL(0.512 ns) 7.153 ns instruc2main:inst6\|FIFO1_amp\[6\]~141 5 COMB LCCOMB_X26_Y15_N6 1 " "Info: 5: + IC(0.504 ns) + CELL(0.512 ns) = 7.153 ns; Loc. = LCCOMB_X26_Y15_N6; Fanout = 1; COMB Node = 'instruc2main:inst6\|FIFO1_amp\[6\]~141'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.016 ns" { instruc2main:inst6|FIFO1_amp[6]~140 instruc2main:inst6|FIFO1_amp[6]~141 } "NODE_NAME" } } { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.419 ns) + CELL(0.000 ns) 9.572 ns instruc2main:inst6\|FIFO1_amp\[6\]~141clkctrl 6 COMB CLKCTRL_G3 12 " "Info: 6: + IC(2.419 ns) + CELL(0.000 ns) = 9.572 ns; Loc. = CLKCTRL_G3; Fanout = 12; COMB Node = 'instruc2main:inst6\|FIFO1_amp\[6\]~141clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.419 ns" { instruc2main:inst6|FIFO1_amp[6]~141 instruc2main:inst6|FIFO1_amp[6]~141clkctrl } "NODE_NAME" } } { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.449 ns) + CELL(0.178 ns) 11.199 ns instruc2main:inst6\|FIFO1_time\[0\] 7 REG LCCOMB_X23_Y15_N22 7 " "Info: 7: + IC(1.449 ns) + CELL(0.178 ns) = 11.199 ns; Loc. = LCCOMB_X23_Y15_N22; Fanout = 7; REG Node = 'instruc2main:inst6\|FIFO1_time\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.627 ns" { instruc2main:inst6|FIFO1_amp[6]~141clkctrl instruc2main:inst6|FIFO1_time[0] } "NODE_NAME" } } { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.929 ns ( 35.08 % ) " "Info: Total cell delay = 3.929 ns ( 35.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.270 ns ( 64.92 % ) " "Info: Total interconnect delay = 7.270 ns ( 64.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.199 ns" { clk uart_top:inst|uart_core:inst|recv get:inst5|dataout3[5] instruc2main:inst6|FIFO1_amp[6]~140 instruc2main:inst6|FIFO1_amp[6]~141 instruc2main:inst6|FIFO1_amp[6]~141clkctrl instruc2main:inst6|FIFO1_time[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.199 ns" { clk clk~combout uart_top:inst|uart_core:inst|recv get:inst5|dataout3[5] instruc2main:inst6|FIFO1_amp[6]~140 instruc2main:inst6|FIFO1_amp[6]~141 instruc2main:inst6|FIFO1_amp[6]~141clkctrl instruc2main:inst6|FIFO1_time[0] } { 0.000ns 0.000ns 1.656ns 0.869ns 0.373ns 0.504ns 2.419ns 1.449ns } { 0.000ns 1.026ns 0.879ns 0.879ns 0.455ns 0.512ns 0.000ns 0.178ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "I