prev_cmp_serial_uart_top.tan.qmsg

来自「FPGA Cycloneii 系列的」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_amp\[6\] " "Warning: Node \"instruc2main:inst6\|FIFO1_amp\[6\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_amp\[5\] " "Warning: Node \"instruc2main:inst6\|FIFO1_amp\[5\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_amp\[4\] " "Warning: Node \"instruc2main:inst6\|FIFO1_amp\[4\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_amp\[1\] " "Warning: Node \"instruc2main:inst6\|FIFO1_amp\[1\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_amp\[2\] " "Warning: Node \"instruc2main:inst6\|FIFO1_amp\[2\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_amp\[0\] " "Warning: Node \"instruc2main:inst6\|FIFO1_amp\[0\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_amp\[3\] " "Warning: Node \"instruc2main:inst6\|FIFO1_amp\[3\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_time\[2\] " "Warning: Node \"instruc2main:inst6\|FIFO1_time\[2\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_time\[0\] " "Warning: Node \"instruc2main:inst6\|FIFO1_time\[0\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_time\[3\] " "Warning: Node \"instruc2main:inst6\|FIFO1_time\[3\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_time\[1\] " "Warning: Node \"instruc2main:inst6\|FIFO1_time\[1\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "instruc2main:inst6\|FIFO1_time\[4\] " "Warning: Node \"instruc2main:inst6\|FIFO1_time\[4\]\" is a latch" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "23 " "Warning: Found 23 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "uart_top:inst\|bd_generator:inst5\|bd_out " "Info: Detected ripple clock \"uart_top:inst\|bd_generator:inst5\|bd_out\" as buffer" {  } { { "bd_generator.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/bd_generator.v" 36 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "uart_top:inst\|bd_generator:inst5\|bd_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout2\[5\] " "Info: Detected ripple clock \"get:inst5\|dataout2\[5\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout2\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout2\[6\] " "Info: Detected ripple clock \"get:inst5\|dataout2\[6\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout2\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout2\[7\] " "Info: Detected ripple clock \"get:inst5\|dataout2\[7\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout2\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout2\[4\] " "Info: Detected ripple clock \"get:inst5\|dataout2\[4\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout2\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout3\[2\] " "Info: Detected ripple clock \"get:inst5\|dataout3\[2\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout3\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout3\[1\] " "Info: Detected ripple clock \"get:inst5\|dataout3\[1\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout3\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout3\[0\] " "Info: Detected ripple clock \"get:inst5\|dataout3\[0\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout3\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout3\[3\] " "Info: Detected ripple clock \"get:inst5\|dataout3\[3\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout3\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout2\[1\] " "Info: Detected ripple clock \"get:inst5\|dataout2\[1\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout2\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout2\[2\] " "Info: Detected ripple clock \"get:inst5\|dataout2\[2\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout2\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout2\[0\] " "Info: Detected ripple clock \"get:inst5\|dataout2\[0\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout2\[3\] " "Info: Detected ripple clock \"get:inst5\|dataout2\[3\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout2\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout3\[6\] " "Info: Detected ripple clock \"get:inst5\|dataout3\[6\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout3\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout3\[4\] " "Info: Detected ripple clock \"get:inst5\|dataout3\[4\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout3\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout3\[7\] " "Info: Detected ripple clock \"get:inst5\|dataout3\[7\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout3\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "get:inst5\|dataout3\[5\] " "Info: Detected ripple clock \"get:inst5\|dataout3\[5\]\" as buffer" {  } { { "get.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/get.v" 49 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "get:inst5\|dataout3\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "instruc2main:inst6\|FIFO1_amp\[6\]~137 " "Info: Detected gated clock \"instruc2main:inst6\|FIFO1_amp\[6\]~137\" as buffer" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "instruc2main:inst6\|FIFO1_amp\[6\]~137" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "instruc2main:inst6\|FIFO1_amp\[6\]~139 " "Info: Detected gated clock \"instruc2main:inst6\|FIFO1_amp\[6\]~139\" as buffer" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "instruc2main:inst6\|FIFO1_amp\[6\]~139" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "instruc2main:inst6\|FIFO1_amp\[6\]~138 " "Info: Detected gated clock \"instruc2main:inst6\|FIFO1_amp\[6\]~138\" as buffer" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "instruc2main:inst6\|FIFO1_amp\[6\]~138" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "instruc2main:inst6\|FIFO1_amp\[6\]~140 " "Info: Detected gated clock \"instruc2main:inst6\|FIFO1_amp\[6\]~140\" as buffer" {  } { { "instruc2main.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/instruc2main.v" 79 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "instruc2main:inst6\|FIFO1_amp\[6\]~140" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "uart_top:inst\|uart_core:inst\|recv " "Info: Detected ripple clock \"uart_top:inst\|uart_core:inst\|recv\" as buffer" {  } { { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 45 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "uart_top:inst\|uart_core:inst\|recv" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "uart_top:inst\|bd_generator:inst5\|indicator " "Info: Detected ripple clock \"uart_top:inst\|bd_generator:inst5\|indicator\" as buffer" {  } { { "bd_generator.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/bd_generator.v" 37 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "uart_top:inst\|bd_generator:inst5\|indicator" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}