prev_cmp_serial_uart_top.tan.qmsg

来自「FPGA Cycloneii 系列的」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register uart_top:inst\|counter:inst3\|overflow register uart_top:inst\|uart_core:inst\|recv_bus\[6\] 111.64 MHz 8.957 ns Internal " "Info: Clock \"clk\" has Internal fmax of 111.64 MHz between source register \"uart_top:inst\|counter:inst3\|overflow\" and destination register \"uart_top:inst\|uart_core:inst\|recv_bus\[6\]\" (period= 8.957 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.778 ns + Longest register register " "Info: + Longest register to register delay is 1.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_top:inst\|counter:inst3\|overflow 1 REG LCFF_X31_Y15_N31 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y15_N31; Fanout = 5; REG Node = 'uart_top:inst\|counter:inst3\|overflow'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "counter.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/counter.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.402 ns) + CELL(0.178 ns) 0.580 ns uart_top:inst\|uart_core:inst\|Selector9~110 2 COMB LCCOMB_X31_Y15_N14 10 " "Info: 2: + IC(0.402 ns) + CELL(0.178 ns) = 0.580 ns; Loc. = LCCOMB_X31_Y15_N14; Fanout = 10; COMB Node = 'uart_top:inst\|uart_core:inst\|Selector9~110'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.580 ns" { uart_top:inst|counter:inst3|overflow uart_top:inst|uart_core:inst|Selector9~110 } "NODE_NAME" } } { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.758 ns) 1.778 ns uart_top:inst\|uart_core:inst\|recv_bus\[6\] 3 REG LCFF_X30_Y15_N29 4 " "Info: 3: + IC(0.440 ns) + CELL(0.758 ns) = 1.778 ns; Loc. = LCFF_X30_Y15_N29; Fanout = 4; REG Node = 'uart_top:inst\|uart_core:inst\|recv_bus\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.198 ns" { uart_top:inst|uart_core:inst|Selector9~110 uart_top:inst|uart_core:inst|recv_bus[6] } "NODE_NAME" } } { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.936 ns ( 52.64 % ) " "Info: Total cell delay = 0.936 ns ( 52.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.842 ns ( 47.36 % ) " "Info: Total interconnect delay = 0.842 ns ( 47.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.778 ns" { uart_top:inst|counter:inst3|overflow uart_top:inst|uart_core:inst|Selector9~110 uart_top:inst|uart_core:inst|recv_bus[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.778 ns" { uart_top:inst|counter:inst3|overflow uart_top:inst|uart_core:inst|Selector9~110 uart_top:inst|uart_core:inst|recv_bus[6] } { 0.000ns 0.402ns 0.440ns } { 0.000ns 0.178ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.940 ns - Smallest " "Info: - Smallest clock skew is -6.940 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.861 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.602 ns) 2.861 ns uart_top:inst\|uart_core:inst\|recv_bus\[6\] 3 REG LCFF_X30_Y15_N29 4 " "Info: 3: + IC(0.995 ns) + CELL(0.602 ns) = 2.861 ns; Loc. = LCFF_X30_Y15_N29; Fanout = 4; REG Node = 'uart_top:inst\|uart_core:inst\|recv_bus\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.597 ns" { clk~clkctrl uart_top:inst|uart_core:inst|recv_bus[6] } "NODE_NAME" } } { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.90 % ) " "Info: Total cell delay = 1.628 ns ( 56.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.233 ns ( 43.10 % ) " "Info: Total interconnect delay = 1.233 ns ( 43.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { clk clk~clkctrl uart_top:inst|uart_core:inst|recv_bus[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { clk clk~combout clk~clkctrl uart_top:inst|uart_core:inst|recv_bus[6] } { 0.000ns 0.000ns 0.238ns 0.995ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.801 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.255 ns) + CELL(0.879 ns) 4.160 ns uart_top:inst\|bd_generator:inst5\|indicator 2 REG LCFF_X39_Y16_N19 2 " "Info: 2: + IC(2.255 ns) + CELL(0.879 ns) = 4.160 ns; Loc. = LCFF_X39_Y16_N19; Fanout = 2; REG Node = 'uart_top:inst\|bd_generator:inst5\|indicator'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.134 ns" { clk uart_top:inst|bd_generator:inst5|indicator } "NODE_NAME" } } { "bd_generator.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/bd_generator.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(0.545 ns) 6.554 ns uart_top:inst\|switcher:inst4\|dout 3 COMB LCCOMB_X24_Y20_N14 1 " "Info: 3: + IC(1.849 ns) + CELL(0.545 ns) = 6.554 ns; Loc. = LCCOMB_X24_Y20_N14; Fanout = 1; COMB Node = 'uart_top:inst\|switcher:inst4\|dout'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.394 ns" { uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout } "NODE_NAME" } } { "switcher.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/switcher.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.657 ns) + CELL(0.000 ns) 8.211 ns uart_top:inst\|switcher:inst4\|dout~clkctrl 4 COMB CLKCTRL_G9 5 " "Info: 4: + IC(1.657 ns) + CELL(0.000 ns) = 8.211 ns; Loc. = CLKCTRL_G9; Fanout = 5; COMB Node = 'uart_top:inst\|switcher:inst4\|dout~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl } "NODE_NAME" } } { "switcher.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/switcher.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 9.801 ns uart_top:inst\|counter:inst3\|overflow 5 REG LCFF_X31_Y15_N31 5 " "Info: 5: + IC(0.988 ns) + CELL(0.602 ns) = 9.801 ns; Loc. = LCFF_X31_Y15_N31; Fanout = 5; REG Node = 'uart_top:inst\|counter:inst3\|overflow'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "counter.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/counter.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.052 ns ( 31.14 % ) " "Info: Total cell delay = 3.052 ns ( 31.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.749 ns ( 68.86 % ) " "Info: Total interconnect delay = 6.749 ns ( 68.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.801 ns" { clk uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.801 ns" { clk clk~combout uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } { 0.000ns 0.000ns 2.255ns 1.849ns 1.657ns 0.988ns } { 0.000ns 1.026ns 0.879ns 0.545ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { clk clk~clkctrl uart_top:inst|uart_core:inst|recv_bus[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { clk clk~combout clk~clkctrl uart_top:inst|uart_core:inst|recv_bus[6] } { 0.000ns 0.000ns 0.238ns 0.995ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.801 ns" { clk uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.801 ns" { clk clk~combout uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } { 0.000ns 0.000ns 2.255ns 1.849ns 1.657ns 0.988ns } { 0.000ns 1.026ns 0.879ns 0.545ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "counter.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/counter.v" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 109 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.778 ns" { uart_top:inst|counter:inst3|overflow uart_top:inst|uart_core:inst|Selector9~110 uart_top:inst|uart_core:inst|recv_bus[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.778 ns" { uart_top:inst|counter:inst3|overflow uart_top:inst|uart_core:inst|Selector9~110 uart_top:inst|uart_core:inst|recv_bus[6] } { 0.000ns 0.402ns 0.440ns } { 0.000ns 0.178ns 0.758ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { clk clk~clkctrl uart_top:inst|uart_core:inst|recv_bus[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { clk clk~combout clk~clkctrl uart_top:inst|uart_core:inst|recv_bus[6] } { 0.000ns 0.000ns 0.238ns 0.995ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.801 ns" { clk uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.801 ns" { clk clk~combout uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } { 0.000ns 0.000ns 2.255ns 1.849ns 1.657ns 0.988ns } { 0.000ns 1.026ns 0.879ns 0.545ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 71 " "Warning: Circuit may not operate. Detected 71 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "uart_top:inst\|uart_core:inst\|ce_parts uart_top:inst\|counter:inst3\|overflow clk 6.137 ns " "Info: Found hold time violation between source  pin or register \"uart_top:inst\|uart_core:inst\|ce_parts\" and destination pin or register \"uart_top:inst\|counter:inst3\|overflow\" for clock \"clk\" (Hold time is 6.137 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.940 ns + Largest " "Info: + Largest clock skew is 6.940 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.801 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.801 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.255 ns) + CELL(0.879 ns) 4.160 ns uart_top:inst\|bd_generator:inst5\|indicator 2 REG LCFF_X39_Y16_N19 2 " "Info: 2: + IC(2.255 ns) + CELL(0.879 ns) = 4.160 ns; Loc. = LCFF_X39_Y16_N19; Fanout = 2; REG Node = 'uart_top:inst\|bd_generator:inst5\|indicator'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.134 ns" { clk uart_top:inst|bd_generator:inst5|indicator } "NODE_NAME" } } { "bd_generator.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/bd_generator.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.849 ns) + CELL(0.545 ns) 6.554 ns uart_top:inst\|switcher:inst4\|dout 3 COMB LCCOMB_X24_Y20_N14 1 " "Info: 3: + IC(1.849 ns) + CELL(0.545 ns) = 6.554 ns; Loc. = LCCOMB_X24_Y20_N14; Fanout = 1; COMB Node = 'uart_top:inst\|switcher:inst4\|dout'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.394 ns" { uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout } "NODE_NAME" } } { "switcher.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/switcher.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.657 ns) + CELL(0.000 ns) 8.211 ns uart_top:inst\|switcher:inst4\|dout~clkctrl 4 COMB CLKCTRL_G9 5 " "Info: 4: + IC(1.657 ns) + CELL(0.000 ns) = 8.211 ns; Loc. = CLKCTRL_G9; Fanout = 5; COMB Node = 'uart_top:inst\|switcher:inst4\|dout~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.657 ns" { uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl } "NODE_NAME" } } { "switcher.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/switcher.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.988 ns) + CELL(0.602 ns) 9.801 ns uart_top:inst\|counter:inst3\|overflow 5 REG LCFF_X31_Y15_N31 5 " "Info: 5: + IC(0.988 ns) + CELL(0.602 ns) = 9.801 ns; Loc. = LCFF_X31_Y15_N31; Fanout = 5; REG Node = 'uart_top:inst\|counter:inst3\|overflow'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "counter.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/counter.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.052 ns ( 31.14 % ) " "Info: Total cell delay = 3.052 ns ( 31.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.749 ns ( 68.86 % ) " "Info: Total interconnect delay = 6.749 ns ( 68.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.801 ns" { clk uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.801 ns" { clk clk~combout uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } { 0.000ns 0.000ns 2.255ns 1.849ns 1.657ns 0.988ns } { 0.000ns 1.026ns 0.879ns 0.545ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.861 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns clk 1 CLK PIN_L1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 4; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { clk clk~clkctrl } "NODE_NAME" } } { "serial_uart_top.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.bdf" { { 32 0 168 48 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.602 ns) 2.861 ns uart_top:inst\|uart_core:inst\|ce_parts 3 REG LCFF_X31_Y15_N9 24 " "Info: 3: + IC(0.995 ns) + CELL(0.602 ns) = 2.861 ns; Loc. = LCFF_X31_Y15_N9; Fanout = 24; REG Node = 'uart_top:inst\|uart_core:inst\|ce_parts'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.597 ns" { clk~clkctrl uart_top:inst|uart_core:inst|ce_parts } "NODE_NAME" } } { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.90 % ) " "Info: Total cell delay = 1.628 ns ( 56.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.233 ns ( 43.10 % ) " "Info: Total interconnect delay = 1.233 ns ( 43.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { clk clk~clkctrl uart_top:inst|uart_core:inst|ce_parts } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { clk clk~combout clk~clkctrl uart_top:inst|uart_core:inst|ce_parts } { 0.000ns 0.000ns 0.238ns 0.995ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.801 ns" { clk uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.801 ns" { clk clk~combout uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } { 0.000ns 0.000ns 2.255ns 1.849ns 1.657ns 0.988ns } { 0.000ns 1.026ns 0.879ns 0.545ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { clk clk~clkctrl uart_top:inst|uart_core:inst|ce_parts } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { clk clk~combout clk~clkctrl uart_top:inst|uart_core:inst|ce_parts } { 0.000ns 0.000ns 0.238ns 0.995ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.812 ns - Shortest register register " "Info: - Shortest register to register delay is 0.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns uart_top:inst\|uart_core:inst\|ce_parts 1 REG LCFF_X31_Y15_N9 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y15_N9; Fanout = 24; REG Node = 'uart_top:inst\|uart_core:inst\|ce_parts'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { uart_top:inst|uart_core:inst|ce_parts } "NODE_NAME" } } { "uart_core.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/uart_core.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.322 ns) 0.716 ns uart_top:inst\|counter:inst3\|always0~47 2 COMB LCCOMB_X31_Y15_N30 1 " "Info: 2: + IC(0.394 ns) + CELL(0.322 ns) = 0.716 ns; Loc. = LCCOMB_X31_Y15_N30; Fanout = 1; COMB Node = 'uart_top:inst\|counter:inst3\|always0~47'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.716 ns" { uart_top:inst|uart_core:inst|ce_parts uart_top:inst|counter:inst3|always0~47 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 0.812 ns uart_top:inst\|counter:inst3\|overflow 3 REG LCFF_X31_Y15_N31 5 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 0.812 ns; Loc. = LCFF_X31_Y15_N31; Fanout = 5; REG Node = 'uart_top:inst\|counter:inst3\|overflow'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { uart_top:inst|counter:inst3|always0~47 uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "counter.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/counter.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.418 ns ( 51.48 % ) " "Info: Total cell delay = 0.418 ns ( 51.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.394 ns ( 48.52 % ) " "Info: Total interconnect delay = 0.394 ns ( 48.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.812 ns" { uart_top:inst|uart_core:inst|ce_parts uart_top:inst|counter:inst3|always0~47 uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.812 ns" { uart_top:inst|uart_core:inst|ce_parts uart_top:inst|counter:inst3|always0~47 uart_top:inst|counter:inst3|overflow } { 0.000ns 0.394ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "counter.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/counter.v" 36 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.801 ns" { clk uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "9.801 ns" { clk clk~combout uart_top:inst|bd_generator:inst5|indicator uart_top:inst|switcher:inst4|dout uart_top:inst|switcher:inst4|dout~clkctrl uart_top:inst|counter:inst3|overflow } { 0.000ns 0.000ns 2.255ns 1.849ns 1.657ns 0.988ns } { 0.000ns 1.026ns 0.879ns 0.545ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.861 ns" { clk clk~clkctrl uart_top:inst|uart_core:inst|ce_parts } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.861 ns" { clk clk~combout clk~clkctrl uart_top:inst|uart_core:inst|ce_parts } { 0.000ns 0.000ns 0.238ns 0.995ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.812 ns" { uart_top:inst|uart_core:inst|ce_parts uart_top:inst|counter:inst3|always0~47 uart_top:inst|counter:inst3|overflow } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.812 ns" { uart_top:inst|uart_core:inst|ce_parts uart_top:inst|counter:inst3|always0~47 uart_top:inst|counter:inst3|overflow } { 0.000ns 0.394ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}