singleclocksynchronousdesignmetriccntr.txt

用VHDL 设计的单时钟同步十进制可逆计数器的设计

7、单时钟，同步十进制可逆计数器的设计
源程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity 1s190 is
     port(cp,s,ld,ud,d0,d1,d2,d3:in std_logic; 
           c:out std_logic;
           q:out std_logic_vector(3 downto 0)); 
end 1s190;
architecture rtl of 1s190 is
     signal y,d:std_logic_vector(3 downto 0); 
begin
process(cp,s,ld,ud)
begin
    d<=d3&d2&d1&d0;
    if(ld='0')then
       y<=d;
      c<='0';
      elsif(cp'event and cp='1')then
     if s='0'then
    if ud='0'then
   if(y="1001")then
      y<="0000";
      c<='1';
    else
    y<=y+1;
    c<='0';
    end if;
    elsif ud='1'then
    if(y='0000')then
     y<="1001";
      c<='1';
    else
     y<=y-1;
     c<='0';
    end if;
   end if;
  elsif s='1'then
  y<=y;
  end if;
   end if;
   end process;
 q<=y;
end rtl;