dianzhen.map.rpt

实现一个10秒倒计时电路

; state.s0 ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ;
; state.s1 ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 1        ;
; state.s2 ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 1        ;
; state.s3 ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 1        ;
; state.s4 ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 1        ;
; state.s5 ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 1        ;
; state.s6 ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ;
; state.s7 ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ;
+----------+----------+----------+----------+----------+----------+----------+----------+----------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                      ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |dianzhen                  ; 257 (257)   ; 117          ; 0          ; 40   ; 0            ; 140 (140)    ; 51 (51)           ; 66 (66)          ; 71 (71)         ; |dianzhen           ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/yaning8/ya3/db/dianzhen.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------+-------------------------+
; File Name    ; Used in Netlist         ;
+--------------+-------------------------+
; dianzhen.vhd ; yes                     ;
+--------------+-------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 257     ;
; Total combinational functions     ; 206     ;
; Total 4-input functions           ; 70      ;
; Total 3-input functions           ; 42      ;
; Total 2-input functions           ; 23      ;
; Total 1-input functions           ; 71      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 117     ;
; Total logic cells in carry chains ; 71      ;
; I/O pins                          ; 40      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 64      ;
; Total fan-out                     ; 798     ;
; Average fan-out                   ; 2.69    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Fri Dec 26 11:28:19 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off dianzhen -c dianzhen
Info: Found 2 design units, including 1 entities, in source file dianzhen.vhd
    Info: Found design unit 1: dianzhen-rtl
    Info: Found entity 1: dianzhen
Warning: VHDL Process Statement warning at dianzhen.vhd(112): signal clk4 is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at dianzhen.vhd(275): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(289): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(303): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(317): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(331): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(345): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(359): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(373): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(387): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(401): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(415): OTHERS choice is never selected
Info: VHDL Case Statement information at dianzhen.vhd(437): OTHERS choice is never selected
Warning: Reduced register flag1[31] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[30] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[29] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[28] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[27] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[26] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[25] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[24] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[23] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[22] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[21] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[20] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[19] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[18] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[17] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[16] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[15] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[14] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[13] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[12] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[11] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[10] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[9] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[8] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[7] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[6] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[5] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[4] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[3] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[2] with stuck data_in port to stuck value GND
Warning: Reduced register flag1[1] with stuck data_in port to stuck value GND
Warning: Reduced register col[7]~reg0 with stuck data_in port to stuck value GND
Warning: Reduced register col[6]~reg0 with stuck data_in port to stuck value GND
Warning: Reduced register col[0]~reg0 with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register q[0]~reg0 merged to single register q[7]~reg0
    Info: Duplicate register q[1]~reg0 merged to single register q[6]~reg0
    Info: Duplicate register q[2]~reg0 merged to single register q[5]~reg0
    Info: Duplicate register q[3]~reg0 merged to single register q[4]~reg0
Info: State machine |dianzhen|state contains 8 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |dianzhen|state
Info: Encoding result for state machine |dianzhen|state
    Info: Completed encoding using 8 state bits
        Info: Encoded state bit state~81
        Info: Encoded state bit state~80
        Info: Encoded state bit state~79
        Info: Encoded state bit state~78
        Info: Encoded state bit state~77
        Info: Encoded state bit state~76
        Info: Encoded state bit state~75
        Info: Encoded state bit state~74
    Info: State |dianzhen|state.s0 uses code string 00000000
    Info: State |dianzhen|state.s1 uses code string 00000011
    Info: State |dianzhen|state.s2 uses code string 00000101
    Info: State |dianzhen|state.s3 uses code string 00001001
    Info: State |dianzhen|state.s4 uses code string 00010001
    Info: State |dianzhen|state.s5 uses code string 00100001
    Info: State |dianzhen|state.s6 uses code string 01000001
    Info: State |dianzhen|state.s7 uses code string 10000001
Warning: Output pins are stuck at VCC or GND
    Warning: Pin col[7] stuck at GND
    Warning: Pin col[6] stuck at GND
    Warning: Pin col[0] stuck at GND
Info: Implemented 297 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 37 output pins
    Info: Implemented 257 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 39 warnings
    Info: Processing ended: Fri Dec 26 11:28:22 2008
    Info: Elapsed time: 00:00:03