📄 wuxinkun.rpt
字号:
_EQ046 = A0 & A2 & !A3 & B0 & B1 & B2 & !B3 & _LC049
# !A1 & A3 & B0 & B1 & B2 & !B3 & _LC049
# A0 & !A2 & A3 & B0 & B1 & B2 & _LC049
# !A0 & A1 & !A2 & B0 & B1 & !_LC049
# A0 & A1 & !A2 & !B0 & B1 & !_LC049;
-- Node name is '|7483:34|~21~5'
-- Equation name is '_LC051', type is buried
-- synthesized logic cell
_LC051 = LCELL( _EQ047 $ GND);
_EQ047 = !A0 & !A1 & !A3 & !B3 & !_LC049
# !A3 & !B0 & !B1 & !B3 & !_LC049
# !A2 & !A3 & !_LC049
# !A2 & !A3 & !B1 & !_LC049
# !A0 & !A2 & !A3 & !_LC049;
-- Node name is '|7483:34|~21~6'
-- Equation name is '_LC087', type is buried
-- synthesized logic cell
_LC087 = LCELL( _EQ048 $ GND);
_EQ048 = !A2 & A3 & !B1 & B2 & _LC049
# !A0 & !A2 & A3 & !B0 & B2 & _LC049
# !A1 & !A2 & A3 & B2 & _LC049
# !A2 & !B2 & !_LC049;
-- Node name is '|7483:34|~22~1'
-- Equation name is '_LC085', type is buried
-- synthesized logic cell
_LC085 = LCELL( _EQ049 $ _EQ050);
_EQ049 = A3 & B3 & !_LC042 & !_LC059;
_EQ050 = !_LC042 & !_LC059;
-- Node name is '|7483:34|~34~1'
-- Equation name is '_LC036', type is buried
-- synthesized logic cell
_LC036 = LCELL( _EQ051 $ VCC);
_EQ051 = !_LC051 & !_LC071 & !_LC072 & !_LC080 & !_LC081 & !_LC083 & _X012 &
_X013;
_X012 = EXP(!A1 & !A2 & !A3 & !_LC049);
_X013 = EXP(!B2 & !B3 & !_LC049);
-- Node name is '|7483:34|~34~2'
-- Equation name is '_LC071', type is buried
-- synthesized logic cell
_LC071 = LCELL( _EQ052 $ GND);
_EQ052 = A0 & !A1 & A2 & B0 & B1 & B2 & !B3 & _LC049
# A0 & !A2 & A3 & B0 & B1 & B2 & _LC049 & !_LC090
# A0 & !A2 & A3 & B0 & B1 & B2 & !B3 & _LC049
# !A0 & A1 & !A2 & B0 & B1 & !_LC049 & !_LC090
# A0 & A1 & !A2 & !B0 & B1 & !_LC049 & !_LC090;
-- Node name is '|7483:34|~34~3'
-- Equation name is '_LC072', type is buried
-- synthesized logic cell
_LC072 = LCELL( _EQ053 $ GND);
_EQ053 = A0 & A1 & !A2 & !B0 & B1 & !B3 & !_LC049
# !A0 & A1 & !A2 & B0 & B1 & !B3 & !_LC049
# !A2 & A3 & !B1 & B2 & _LC049 & !_LC090
# !A2 & A3 & !B1 & B2 & !B3 & _LC049
# !A0 & !A2 & A3 & !B0 & B2 & _LC049 & !_LC090;
-- Node name is '|7483:34|~34~4'
-- Equation name is '_LC080', type is buried
-- synthesized logic cell
_LC080 = LCELL( _EQ054 $ GND);
_EQ054 = !A0 & !A2 & A3 & !B0 & B2 & !B3 & _LC049
# !A1 & !A2 & A3 & B2 & _LC049 & !_LC090
# !A1 & !A2 & A3 & B2 & !B3 & _LC049
# !A2 & !A3 & !B2 & !_LC049
# !A2 & !B2 & !_LC049 & !_LC090;
-- Node name is '|7483:34|~45~1~2'
-- Equation name is '_LC091', type is buried
-- synthesized logic cell
_LC091 = LCELL( _EQ055 $ GND);
_EQ055 = A0 & A1 & A2 & !A3 & B0 & !B1 & B2 & _LC018 & _LC049
# A0 & !A1 & A2 & B0 & B1 & B2 & _LC018 & _LC049
# A1 & A2 & !A3 & !B0 & B1 & B2 & _LC018 & _LC049
# A0 & A1 & !A2 & A3 & !B0 & B1 & B2 & _LC018
# A0 & !A1 & A2 & B0 & !B1 & B2 & _LC018 & !_LC049;
-- Node name is '|7483:34|~45~1~3'
-- Equation name is '_LC077', type is buried
-- synthesized logic cell
_LC077 = LCELL( _EQ056 $ GND);
_EQ056 = A1 & A2 & A3 & B0 & B2 & _LC018 & !_LC049
# !A1 & A3 & !B0 & !B1 & B2 & !_LC018 & _LC049
# !A0 & A1 & A2 & A3 & B0 & !_LC049
# !A0 & A1 & !A3 & B1 & B2 & _LC049
# !A2 & A3 & B0 & B1 & B2 & !_LC018;
-- Node name is '|7483:34|~45~1~4'
-- Equation name is '_LC076', type is buried
-- synthesized logic cell
_LC076 = LCELL( _EQ057 $ GND);
_EQ057 = !A0 & !A1 & A3 & B0 & B2 & _LC049
# A2 & A3 & B0 & !B2 & !_LC018 & !_LC049
# !A0 & !A1 & A3 & !B1 & B2 & _LC049
# !A0 & !A2 & B0 & B1 & B2
# A0 & !A2 & B0 & !B2 & !_LC018;
-- Node name is '|7483:34|~45~1~5'
-- Equation name is '_LC050', type is buried
-- synthesized logic cell
_LC050 = LCELL( _EQ058 $ GND);
_EQ058 = !A0 & !A1 & !B0 & B1 & !_LC049
# !A1 & !B0 & B1 & !_LC018 & !_LC049
# !A1 & !A3 & !B0 & !_LC018 & !_LC049
# !A3 & !B0 & !B2 & !_LC018 & !_LC049
# !A0 & !A3 & !B0 & !B2 & !_LC049;
-- Node name is '|7483:34|~45~1~6'
-- Equation name is '_LC069', type is buried
-- synthesized logic cell
_LC069 = LCELL( _EQ059 $ GND);
_EQ059 = !A0 & !A1 & !A3 & !_LC049
# !A2 & !A3 & !B1 & !_LC018
# !A2 & !A3 & !B2 & !_LC018
# !A2 & !B0 & !B1 & !_LC018
# !A0 & !A2 & !B0 & !B1;
-- Node name is '|7483:34|~45~1~7'
-- Equation name is '_LC052', type is buried
-- synthesized logic cell
_LC052 = LCELL( _EQ060 $ GND);
_EQ060 = !B1 & !B2 & !_LC018 & !_LC049
# !A0 & !B1 & !B2 & !_LC049
# !A0 & !A2 & !B1 & !B2
# !A0 & !A2 & !A3
# !A1 & !B2 & !_LC018 & !_LC049;
-- Node name is '|7483:34|~45~1~8'
-- Equation name is '_LC079', type is buried
-- synthesized logic cell
_LC079 = LCELL( _EQ061 $ GND);
_EQ061 = !A0 & !A1 & !B2 & !_LC049
# !A1 & !A2 & !_LC018
# !A1 & A2 & A3 & !B0 & B1 & B2 & !_LC049
# A0 & !A1 & A3 & B0 & !B1 & !_LC049
# !A1 & A2 & B0 & !B2 & !_LC049;
-- Node name is '|7483:34|~45~1~9'
-- Equation name is '_LC063', type is buried
-- synthesized logic cell
_LC063 = LCELL( _EQ062 $ GND);
_EQ062 = !A1 & !B1 & !B2 & !_LC049
# !A1 & !A2 & !B1
# !A0 & A1 & A2 & A3 & B0 & !_LC018 & !_LC049
# !A0 & A1 & !A3 & B1 & B2 & !_LC018 & _LC049
# !A0 & !A1 & A3 & B0 & B2 & !_LC018 & _LC049;
-- Node name is '|7483:34|~45~1~10'
-- Equation name is '_LC094', type is buried
-- synthesized logic cell
_LC094 = LCELL( _EQ063 $ GND);
_EQ063 = !A0 & !A1 & A3 & !B1 & B2 & !_LC018 & _LC049
# A0 & A1 & !B0 & B1 & B2 & !B3 & _LC018
# !A0 & !A2 & B0 & B1 & B2 & !_LC018
# !A0 & !A1 & !B0 & B1 & !_LC018 & !_LC049
# !A0 & !A3 & !B0 & !B2 & !_LC018 & !_LC049;
-- Node name is '|7483:34|~45~1~11'
-- Equation name is '_LC093', type is buried
-- synthesized logic cell
_LC093 = LCELL( _EQ064 $ GND);
_EQ064 = A0 & A2 & B0 & B2 & !B3 & _LC018
# !A0 & !A2 & !B0 & !B1 & !_LC018
# !A0 & !A2 & !B1 & !B2 & !_LC018
# !A0 & !A1 & !A3 & !_LC018 & !_LC049
# !A0 & !B1 & !B2 & !_LC018 & !_LC049;
-- Node name is '|7483:34|~45~1~12'
-- Equation name is '_LC062', type is buried
-- synthesized logic cell
_LC062 = LCELL( _EQ065 $ GND);
_EQ065 = !A0 & !A2 & !A3 & !_LC018
# !A0 & !A1 & !B2 & !_LC018 & !_LC049
# !A2 & B0 & !B3 & !_LC018
# !A0 & !A1 & !A2 & !_LC018
# !A1 & !B0 & !B3 & !_LC018;
-- Node name is '|7483:34|~52~1'
-- Equation name is '_LC005', type is buried
-- synthesized logic cell
_LC005 = LCELL( _EQ066 $ VCC);
_EQ066 = !_LC040 & !_LC054 & !_LC058 & !_LC065 & !_LC078 & _X017;
_X017 = EXP(!A1 & !A2 & !B1 & !B3);
-- Node name is '|7483:34|~52~2'
-- Equation name is '_LC054', type is buried
-- synthesized logic cell
_LC054 = LCELL( _EQ067 $ GND);
_EQ067 = A0 & !A1 & !A3 & B0 & B1 & B2 & _LC049
# A0 & A1 & !A2 & A3 & !B0 & B2 & !B3
# !A1 & A2 & A3 & !B0 & B1 & B2 & !B3
# A0 & A1 & A3 & B0 & B1 & !B3
# !A0 & A1 & B0 & B1 & B2 & !B3;
-- Node name is '|7483:34|~52~3'
-- Equation name is '_LC040', type is buried
-- synthesized logic cell
_LC040 = LCELL( _EQ068 $ GND);
_EQ068 = A0 & A1 & !A2 & B0 & !B2 & !B3
# A0 & !A1 & !A3 & B0 & B1 & !B3
# A0 & !A1 & A3 & B0 & !B1 & !B3
# A0 & A1 & !A3 & B0 & !B1 & !B3
# A1 & A2 & !A3 & !B0 & B1 & !B3;
-- Node name is '|7483:34|~52~4'
-- Equation name is '_LC058', type is buried
-- synthesized logic cell
_LC058 = LCELL( _EQ069 $ GND);
_EQ069 = A1 & A2 & A3 & B0 & !B3
# !A1 & A2 & B0 & !B2 & !B3
# !A1 & !A3 & !B2 & !_LC049
# !A3 & !B0 & !B2 & !B3
# !A0 & !A2 & !A3 & !B3;
-- Node name is '|7483:34|~52~5'
-- Equation name is '_LC078', type is buried
-- synthesized logic cell
_LC078 = LCELL( _EQ070 $ GND);
_EQ070 = !A1 & A2 & A3 & !B0 & B1 & B2 & !_LC049 & !_LC090
# A0 & !A1 & A3 & B0 & !B1 & !_LC049 & !_LC090
# !A1 & A2 & B0 & !B2 & !_LC049 & !_LC090
# !A1 & !B1 & !B2 & !_LC049 & !_LC090
# !A1 & !A2 & !B1 & !_LC090;
-- Node name is '|7483:34|~52~6'
-- Equation name is '_LC065', type is buried
-- synthesized logic cell
_LC065 = LCELL( _EQ071 $ GND);
_EQ071 = !A2 & !B0 & !B1 & !B3
# !A1 & !A2 & !A3
# !B1 & !B2 & !B3;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X002 occurs in LABs B, F
-- _X012 occurs in LABs C, F
-- _X013 occurs in LABs C, F
Project Information h:\ex1\wuxinkun.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,300K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -