wuxinkun.rpt

高速乘法器 高速乘法器 高速乘法器 高速乘法器

5    -> * * | - * * * * * | <-- B0
13   -> * * | * * * * * * | <-- B1
4    -> * * | - * * * * * | <-- B2
LC34 -> - * | - * - - - - | <-- |7483:33|~29~2
LC35 -> - * | - * - - - - | <-- |7483:33|~29~3
LC61 -> * - | - * - - - - | <-- |7483:33|S1~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               h:\ex1\wuxinkun.rpt
wuxinkun

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC37 PS
        | +----------------------------- LC41 P0
        | | +--------------------------- LC42 |7483:33|~2~3
        | | | +------------------------- LC34 |7483:33|~29~2
        | | | | +----------------------- LC35 |7483:33|~29~3
        | | | | | +--------------------- LC36 |7483:34|~34~1
        | | | | | | +------------------- LC48 |7483:34|S1~1
        | | | | | | | +----------------- LC45 |7483:34|S2~1
        | | | | | | | | +--------------- LC46 |7483:34|S2~2
        | | | | | | | | | +------------- LC47 |7483:34|S2~3
        | | | | | | | | | | +----------- LC38 |7483:34|S2~4
        | | | | | | | | | | | +--------- LC39 |7483:34|S2~5
        | | | | | | | | | | | | +------- LC33 |7483:34|S3~3
        | | | | | | | | | | | | | +----- LC44 |7483:34|S3~5
        | | | | | | | | | | | | | | +--- LC43 |7483:34|S3~7
        | | | | | | | | | | | | | | | +- LC40 |7483:34|~52~3
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'C':

Pin
23   -> * - - - - - - - - - - - - - - - | - - * - - - | <-- AS
9    -> - * * * - - * * * * * * * * - * | - * * * * * | <-- A0
12   -> - - * * * * * * * * * * * * * * | * * * * * * | <-- A1
10   -> - - * * * * * * * * * * - - * * | * * * * * * | <-- A2
8    -> - - * * * * - * * * * * * * * * | - * * * * * | <-- A3
22   -> * - - - - - - - - - - - - - - - | - - * - - - | <-- BS
5    -> - * * * * - * * * * * * * * * * | - * * * * * | <-- B0
13   -> - - * * * - * * * * * * * * * * | * * * * * * | <-- B1
4    -> - - * * * * * * * * * * * - * * | - * * * * * | <-- B2
7    -> - - - - - * * * * * * * - - * * | * - * * * * | <-- B3
LC49 -> - - * - - * - - - - - - * * * - | - - * * * * | <-- |7483:32|C4
LC95 -> - - - - - - - - - - - - * * * - | - - * - - - | <-- |7483:34|~21~1
LC81 -> - - - - - * - - - - - - - - - - | - - * - - * | <-- |7483:34|~21~2
LC83 -> - - - - - * - - - - - - - - - - | - - * - - * | <-- |7483:34|~21~3
LC51 -> - - - - - * - - - - - - - - - - | - - * - - * | <-- |7483:34|~21~5
LC71 -> - - - - - * - - - - - - - - - - | - - * - - - | <-- |7483:34|~34~2
LC72 -> - - - - - * - - - - - - - - - - | - - * - - - | <-- |7483:34|~34~3
LC80 -> - - - - - * - - - - - - - - - - | - - * - - - | <-- |7483:34|~34~4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               h:\ex1\wuxinkun.rpt
wuxinkun

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC57 P1
        | +----------------------------- LC64 P3
        | | +--------------------------- LC56 P4
        | | | +------------------------- LC53 P5
        | | | | +----------------------- LC49 |7483:32|C4
        | | | | | +--------------------- LC59 |7483:33|~2~2
        | | | | | | +------------------- LC61 |7483:33|S1~1
        | | | | | | | +----------------- LC51 |7483:34|~21~5
        | | | | | | | | +--------------- LC55 |7483:34|S2~6
        | | | | | | | | | +------------- LC60 |7483:34|S3~6
        | | | | | | | | | | +----------- LC50 |7483:34|~45~1~5
        | | | | | | | | | | | +--------- LC52 |7483:34|~45~1~7
        | | | | | | | | | | | | +------- LC63 |7483:34|~45~1~9
        | | | | | | | | | | | | | +----- LC62 |7483:34|~45~1~12
        | | | | | | | | | | | | | | +--- LC54 |7483:34|~52~2
        | | | | | | | | | | | | | | | +- LC58 |7483:34|~52~4
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'D':
LC49 -> - - - - - * - * - - * * * * * * | - - * * * * | <-- |7483:32|C4
LC55 -> - - * - - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S2~6
LC60 -> - - - * - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S3~6

Pin
9    -> * * * * * * * * * * * * * * * * | - * * * * * | <-- A0
12   -> * - * * * * * * * * * * * * * * | * * * * * * | <-- A1
10   -> - - * - * * * * * * - * * * * * | * * * * * * | <-- A2
8    -> - - * - * * - * - * * * * * * * | - * * * * * | <-- A3
5    -> * - * - * * * * * * * - * * * * | - * * * * * | <-- B0
13   -> * - * - * * * * * * * * * - * - | * * * * * * | <-- B1
4    -> - * * * - * * - * - * * * * * * | - * * * * * | <-- B2
7    -> - * * * - - - * * * - - - * * * | * - * * * * | <-- B3
LC18 -> - * * * - - - - * * * * * * - - | - - - * * * | <-- |7483:33|~29~1
LC48 -> - * - - - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S1~1
LC45 -> - - * - - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S2~1
LC46 -> - - * - - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S2~2
LC47 -> - - * - - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S2~3
LC38 -> - - * - - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S2~4
LC39 -> - - * - - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S2~5
LC92 -> - - - * - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S3~1
LC86 -> - - - * - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S3~2
LC33 -> - - - * - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S3~3
LC82 -> - - - * - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S3~4
LC44 -> - - - * - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S3~5
LC43 -> - - - * - - - - - - - - - - - - | - - - * - - | <-- |7483:34|S3~7


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               h:\ex1\wuxinkun.rpt
wuxinkun

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                         Logic cells placed in LAB 'E'
        +------------------------------- LC67 P7
        | +----------------------------- LC66 |7483:34|~2~2
        | | +--------------------------- LC68 |7483:34|~2~3
        | | | +------------------------- LC70 |7483:34|~2~4
        | | | | +----------------------- LC73 |7483:34|~2~5
        | | | | | +--------------------- LC74 |7483:34|~2~6
        | | | | | | +------------------- LC75 |7483:34|~2~7
        | | | | | | | +----------------- LC71 |7483:34|~34~2
        | | | | | | | | +--------------- LC72 |7483:34|~34~3
        | | | | | | | | | +------------- LC80 |7483:34|~34~4
        | | | | | | | | | | +----------- LC77 |7483:34|~45~1~3
        | | | | | | | | | | | +--------- LC76 |7483:34|~45~1~4
        | | | | | | | | | | | | +------- LC69 |7483:34|~45~1~6
        | | | | | | | | | | | | | +----- LC79 |7483:34|~45~1~8
        | | | | | | | | | | | | | | +--- LC78 |7483:34|~52~5
        | | | | | | | | | | | | | | | +- LC65 |7483:34|~52~6
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'E':
LC66 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |7483:34|~2~2
LC68 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |7483:34|~2~3
LC70 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |7483:34|~2~4
LC73 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |7483:34|~2~5
LC74 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |7483:34|~2~6
LC75 -> * - - - - - - - - - - - - - - - | - - - - * - | <-- |7483:34|~2~7

Pin
9    -> * * * * * * * * * * * * * * * - | - * * * * * | <-- A0
12   -> - * * * * * * * * * * * * * * * | * * * * * * | <-- A1
10   -> * * * * * * * * * * * * * * * * | * * * * * * | <-- A2
8    -> * * * * * * * * * * * * * * * * | - * * * * * | <-- A3
5    -> - * * * * * * * * * * * * * * * | - * * * * * | <-- B0
13   -> - * * * * * * * * - * * * * * * | * * * * * * | <-- B1
4    -> * * * * * * * * * * * * * * * * | - * * * * * | <-- B2
7    -> * * * * * * * * * * - - - - - * | * - * * * * | <-- B3
LC49 -> * * * * * * * * * * * * * * * - | - - * * * * | <-- |7483:32|C4
LC89 -> - - - - - - * - - - - - - - - - | - - - - * - | <-- |7483:33|~2~1
LC18 -> - - - - - - * - - - * * * * - - | - - - * * * | <-- |7483:33|~29~1
LC90 -> * - - - - - * * * * - - - - * - | - - - - * - | <-- |7483:33|C4
LC85 -> * * * * * * * - - - - - - - - - | - - - - * * | <-- |7483:34|~22~1
LC36 -> * * * * * * * - - - - - - - - - | - - - - * - | <-- |7483:34|~34~1
LC5  -> * * * * * * * - - - - - - - - - | - - - - * - | <-- |7483:34|~52~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               h:\ex1\wuxinkun.rpt
wuxinkun

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                       Logic cells placed in LAB 'F'
        +----------------------------- LC84 P6
        | +--------------------------- LC89 |7483:33|~2~1
        | | +------------------------- LC90 |7483:33|C4
        | | | +----------------------- LC95 |7483:34|~21~1
        | | | | +--------------------- LC81 |7483:34|~21~2
        | | | | | +------------------- LC83 |7483:34|~21~3
        | | | | | | +----------------- LC96 |7483:34|~21~4
        | | | | | | | +--------------- LC87 |7483:34|~21~6
        | | | | | | | | +------------- LC85 |7483:34|~22~1
        | | | | | | | | | +----------- LC92 |7483:34|S3~1
        | | | | | | | | | | +--------- LC86 |7483:34|S3~2
        | | | | | | | | | | | +------- LC82 |7483:34|S3~4
        | | | | | | | | | | | | +----- LC91 |7483:34|~45~1~2
        | | | | | | | | | | | | | +--- LC94 |7483:34|~45~1~10
        | | | | | | | | | | | | | | +- LC93 |7483:34|~45~1~11
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | A B C D E F |     Logic cells that feed LAB 'F':
LC81 -> * - - * - - - - - - - - - - - | - - * - - * | <-- |7483:34|~21~2
LC83 -> * - - * - - - - - - - - - - - | - - * - - * | <-- |7483:34|~21~3
LC96 -> * - - * - - - - - - - - - - - | - - - - - * | <-- |7483:34|~21~4
LC87 -> * - - * - - - - - - - - - - - | - - - - - * | <-- |7483:34|~21~6
LC85 -> * - - - - - - - - - - - - - - | - - - - * * | <-- |7483:34|~22~1
LC91 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~2
LC94 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~10
LC93 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~11

Pin
9    -> * - - - * * * * - * * * * * * | - * * * * * | <-- A0
12   -> * - - * * * * * - * * * * * * | * * * * * * | <-- A1
10   -> * - - * * * * * - * * * * * * | * * * * * * | <-- A2
8    -> * - - * * * * * * * * * * * * | - * * * * * | <-- A3
5    -> * - - - * * * * - * * * * * * | - * * * * * | <-- B0
13   -> * - - - * * * * - * * * * * * | * * * * * * | <-- B1
4    -> * - - * * * * * - * * * * * * | - * * * * * | <-- B2
7    -> * - - * * * * - * * * * - * * | * - * * * * | <-- B3
LC49 -> * - - * * * * * - - - - * * * | - - * * * * | <-- |7483:32|C4
LC59 -> * * * - - - - - * - - - - - - | - - - - - * | <-- |7483:33|~2~2
LC42 -> * * * - - - - - * - - - - - - | - - - - - * | <-- |7483:33|~2~3
LC18 -> * - - - - - - - - * * * * * * | - - - * * * | <-- |7483:33|~29~1
LC51 -> * - - * - - - - - - - - - - - | - - * - - * | <-- |7483:34|~21~5
LC77 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~3
LC76 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~4
LC50 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~5
LC69 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~6
LC52 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~7
LC79 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~8
LC63 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~9
LC62 -> * - - - - - - - - - - - - - - | - - - - - * | <-- |7483:34|~45~1~12
LC54 -> * - - - - - - - - - - - - - - | * - - - - * | <-- |7483:34|~52~2
LC40 -> * - - - - - - - - - - - - - - | * - - - - * | <-- |7483:34|~52~3
LC58 -> * - - - - - - - - - - - - - - | * - - - - * | <-- |7483:34|~52~4
LC65 -> * - - - - - - - - - - - - - - | * - - - - * | <-- |7483:34|~52~6


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               h:\ex1\wuxinkun.rpt
wuxinkun

** EQUATIONS **

AS       : INPUT;
A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
BS       : INPUT;
B0       : INPUT;
B1       : INPUT;
B2       : INPUT;
B3       : INPUT;

-- Node name is 'PS' 
-- Equation name is 'PS', location is LC037, type is output.
 PS      = LCELL( AS $  BS);

-- Node name is 'P0' 
-- Equation name is 'P0', location is LC041, type is output.
 P0      = LCELL( _EQ001 $  GND);
  _EQ001 =  A0 &  B0;

-- Node name is 'P1' 
-- Equation name is 'P1', location is LC057, type is output.
 P1      = LCELL( _EQ002 $  GND);
  _EQ002 = !A0 &  A1 &  B0
         #  A1 &  B0 & !B1
         #  A0 & !A1 &  B1
         #  A0 & !B0 &  B1;

-- Node name is 'P2' 
-- Equation name is 'P2', location is LC021, type is output.
 P2      = LCELL( _EQ003 $  _EQ004);
  _EQ003 = !A0 &  A1 &  A2 &  B0 &  B1 & !_LC061 &  _X001 &  _X002
         #  A0 &  A1 & !B0 &  B1 &  B2 & !_LC061 &  _X001 &  _X002
         #  A0 &  A2 &  B0 &  B2 & !_LC061 &  _X001 &  _X002
         #  A0 & !A2 &  B0 & !B2 & !_LC061 &  _X001 &  _X002;
  _X001  = EXP(!B0 & !B1 & !B2);
  _X002  = EXP(!A0 & !A1 & !A2);
  _EQ004 = !_LC061 &  _X001 &  _X002;
  _X001  = EXP(!B0 & !B1 & !B2);
  _X002  = EXP(!A0 & !A1 & !A2);

-- Node name is 'P3' 
-- Equation name is 'P3', location is LC064, type is output.
 P3      = LCELL( _EQ005 $ !_LC018);
  _EQ005 = !_LC048 &  _X003;
  _X003  = EXP( A0 & !B2 &  B3);

-- Node name is 'P4' 
-- Equation name is 'P4', location is LC056, type is output.
 P4      = LCELL( _EQ006 $  _EQ007);
  _EQ006 = !_LC038 & !_LC039 & !_LC045 & !_LC046 & !_LC047 &  _X004 &  _X005 & 
              _X006;
  _X004  = EXP( A2 & !B0 & !B1 &  B2 & !B3);
  _X005  = EXP(!A1 & !A2 &  A3 &  B1);
  _X006  = EXP( A1 & !B1 & !B2 &  B3);
  _EQ007 = !_LC055 &  _X007;
  _X007  = EXP( A0 & !B2 &  B3 &  _LC018);

-- Node name is 'P5' 
-- Equation name is 'P5', location is LC053, type is output.
 P5      = LCELL( _EQ008 $  _EQ009);
  _EQ008 = !_LC033 & !_LC043 & !_LC044;
  _EQ009 = !_LC060 & !_LC082 & !_LC086 & !_LC092 &  _X008;
  _X008  = EXP( A0 &  A1 & !B2 &  B3 &  _LC018);

-- Node name is 'P6' 
-- Equation name is 'P6', location is LC084, type is output.
 P6      = LCELL( _EQ010 $  _EQ011);
  _EQ010 = !_LC042 & !_LC059 & !_LC085
         # !B3 & !_LC085
         # !A3 & !_LC085;
  _EQ011 =  B3 & !_LC040 & !_LC050 & !_LC051 & !_LC052 & !_LC054 & !_LC058 & 
             !_LC062 & !_LC063 & !_LC065 & !_LC069 & !_LC076 & !_LC077 & 
             !_LC079 & !_LC081 & !_LC083 & !_LC087 & !_LC091 & !_LC093 & 
             !_LC094 & !_LC096 &  _X002 &  _X009 &  _X010 &  _X011 &  _X012 & 
              _X013;
  _X002  = EXP(!A0 & !A1 & !A2);
  _X009  = EXP(!B2 & !B3 & !_LC018);
  _X010  = EXP(!A0 & !B3 & !_LC018);
  _X011  = EXP(!B0 & !B1 & !B3 & !_LC018);
  _X012  = EXP(!A1 & !A2 & !A3 & !_LC049);
  _X013  = EXP(!B2 & !B3 & !_LC049);