hanshu.tan.rpt

用FPGA做的DDS函数信号发生器

; Worst-case tsu               ; N/A   ; None          ; 9.435 ns                                       ; m[4]                                                                                                   ; ADDER4B:inst11|S19[17]                                                        ; --         ; cp       ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 253.425 ns                                     ; ADDER4B:inst11|S19[1]                                                                                  ; p[2]                                                                          ; cp         ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 97.237 ns                                      ; xuanzhe                                                                                                ; p[2]                                                                          ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -4.555 ns                                      ; m[0]                                                                                                   ; ADDER4B:inst11|S19[13]                                                        ; --         ; cp       ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; Restricted to 180.05 MHz ( period = 5.554 ns ) ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg7 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[0] ; clk        ; clk      ; 0            ;
; Clock Setup: 'cp'            ; N/A   ; None          ; 251.95 MHz ( period = 3.969 ns )               ; ADDER4B:inst11|S19[2]                                                                                  ; ADDER4B:inst11|S19[17]                                                        ; cp         ; cp       ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                                        ;                                                                               ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C5T144C8        ;      ;    ;             ;
; Timing Models                                         ; Preliminary        ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; cp              ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+