hanshu.tan.rpt

来自「用FPGA做的DDS函数信号发生器」· RPT 代码 · 共 226 行 · 第 1/5 页

; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                   ; To                                                                                                     ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 244.74 MHz ( period = 4.086 ns )                    ; JIA:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_pmg:auto_generated|output_dffea[0]                 ; JIA:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_pmg:auto_generated|output_dffea[23]                ; clk        ; clk      ; None                        ; None                      ; 3.834 ns                ;
; N/A                                     ; 246.91 MHz ( period = 4.050 ns )                    ; JIA:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_pmg:auto_generated|output_dffea[1]                 ; JIA:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_pmg:auto_generated|output_dffea[23]                ; clk        ; clk      ; None                        ; None                      ; 3.798 ns                ;
; N/A                                     ; 250.00 MHz ( period = 4.000 ns )                    ; JIA:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_pmg:auto_generated|output_dffea[0]                 ; JIA:inst3|lpm_add_sub:lpm_add_sub_component|add_sub_pmg:auto_generated|output_dffea[22]                ; clk        ; clk      ; None                        ; None                      ; 3.748 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg0 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg1 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg2 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg3 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg4 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg5 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg6 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg7 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[9]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg0 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg1 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg2 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg3 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg4 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg5 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg6 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg7 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[8]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg0 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg1 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg2 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg3 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg4 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg5 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg6 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg7 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg0 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg1 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg2 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg3 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg4 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg5 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg6 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg7 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[6]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg0 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg1 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg2 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg3 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg4 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg5 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;
; N/A                                     ; Restricted to 180.05 MHz ( period = 5.554 ns )      ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|ram_block1a0~porta_address_reg6 ; sM:inst5|altsyncram:altsyncram_component|altsyncram_pov:auto_generated|q_a[5]                          ; clk        ; clk      ; None                        ; None                      ; 3.641 ns                ;