hanshu.map.rpt

用FPGA做的DDS函数信号发生器

; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; Maximum DSP Block Usage                                            ; -1                 ; -1                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Remove Duplicate Logic                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Maximum Number of M4K Memory Blocks                                ; -1                 ; -1                 ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                            ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                            ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+
; m.vhd                            ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/m.vhd                      ;
; hanshu.bdf                       ; yes             ; User Block Diagram/Schematic File  ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/hanshu.bdf                 ;
; adder4b.vhd                      ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/adder4b.vhd                ;
; chuan.vhd                        ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/chuan.vhd                  ;
; chuan1.vhd                       ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/chuan1.vhd                 ;
; last.vhd                         ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/last.vhd                   ;
; chushu.vhd                       ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/chushu.vhd                 ;
; last1.vhd                        ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/last1.vhd                  ;
; shuju.vhd                        ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/shuju.vhd                  ;
; tr3.vhd                          ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/tr3.vhd                    ;
; tr4.vhd                          ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/tr4.vhd                    ;
; tr5.vhd                          ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/tr5.vhd                    ;
; tr6.vhd                          ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/tr6.vhd                    ;
; tr7.vhd                          ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/tr7.vhd                    ;
; shuchu2.vhd                      ; yes             ; User VHDL File                     ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/shuchu2.vhd                ;
; sM.vhd                           ; yes             ; Other                              ; C:/Documents and Settings/Administrator/桌面/hanshuxinhaogai/sM.vhd                     ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf                              ;
; stratix_ram_block.inc            ; yes             ; Other                              ; d:/altera/quartus51/libraries/megafunctions/stratix_ram_block.inc                       ;
; lpm_mux.inc                      ; yes             ; Other                              ; d:/altera/quartus51/libraries/megafunctions/lpm_mux.inc                                 ;
; lpm_decode.inc                   ; yes             ; Other                              ; d:/altera/quartus51/libraries/megafunctions/lpm_decode.inc                              ;
; aglobal51.inc                    ; yes             ; Other                              ; d:/altera/quartus51/libraries/megafunctions/aglobal51.inc                               ;
; altsyncram.inc                   ; yes             ; Other                              ; d:/altera/quartus51/libraries/megafunctions/altsyncram.inc                              ;
; a_rdenreg.inc                    ; yes             ; Other                              ; d:/altera/quartus51/libraries/megafunctions/a_rdenreg.inc                               ;