clock.qsf

用verilog实现的数字跑表

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		clock_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY paobiao
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:42:23  JANUARY 27, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name USER_LIBRARIES lcd_delay/
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name VERILOG_FILE clock.v
set_global_assignment -name BDF_FILE clock.bdf
set_global_assignment -name VERILOG_FILE clockdivisor.v
set_global_assignment -name VECTOR_WAVEFORM_FILE clock.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE clock.vwf
set_global_assignment -name VERILOG_FILE segmain0.v
set_global_assignment -name TCL_SCRIPT_FILE Tcl_script1.tcl
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
set_location_assignment PIN_91 -to clk
set_location_assignment PIN_161 -to 78ledcom[0]
set_location_assignment PIN_159 -to 78ledcom[1]
set_location_assignment PIN_164 -to 78ledcom[2]
set_location_assignment PIN_162 -to 78ledcom[3]
set_location_assignment PIN_166 -to 78ledcom[4]
set_location_assignment PIN_165 -to 78ledcom[5]
set_location_assignment PIN_156 -to 78leddata[0]
set_location_assignment PIN_150 -to 78leddata[1]
set_location_assignment PIN_140 -to 78leddata[2]
set_location_assignment PIN_141 -to 78leddata[3]
set_location_assignment PIN_155 -to 78leddata[4]
set_location_assignment PIN_157 -to 78leddata[5]
set_location_assignment PIN_139 -to 78leddata[6]
set_location_assignment PIN_149 -to 78leddata[7]
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name VERILOG_FILE paobiao.v
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_92 -to reset_n
set_global_assignment -name VERILOG_FILE shifter.v
set_global_assignment -name VERILOG_FILE key.v
set_location_assignment PIN_110 -to key[3]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top