key.v.bak

用verilog实现的数字跑表

module key(clk,key,en);
input clk,key;
output en;
reg en;
reg[1:0]state,nextstate;
parameter s_0=2'b00,s_1=2'b01,s_2=2'b10,s_3=2'b11;
always@(posedge clk)
begin 
state=nextstate;
end
always@(state or key)
begin
case(state)
s_0:begin en=0;if(!key) nextstate=s_1;else nextstate=s_0;end
s_1:begin en=1;if(!key) nextstate=s_1;else nextstate=s_2;end
s_2:begin en=1;if(!key) nextstate=s_3;else nextstate=s_2;end
s_3:begin en=0;if(!key) nextstate=s_3;else nextstate=s_0;end
default begin en=0;nextstate=s_0;end
endcase
end
endmodule