clock.hier_info

用verilog实现的数字跑表

|paobiao
clk_odd => MSH[3].CLK
clk_odd => MSH[2].CLK
clk_odd => MSH[1].CLK
clk_odd => MSH[0].CLK
clk_odd => MSL[3].CLK
clk_odd => MSL[2].CLK
clk_odd => MSL[1].CLK
clk_odd => MSL[0].CLK
clk_odd => cn1.CLK
pause => MSH[3].ENA
pause => MSH[2].ENA
pause => MSH[1].ENA
pause => MSH[0].ENA
pause => MSL[3].ENA
pause => MSL[2].ENA
pause => MSL[1].ENA
pause => MSL[0].ENA
pause => cn1.ENA
clk_odd10 => count1[2].CLK
clk_odd10 => count1[1].CLK
clk_odd10 => count1[0].CLK
reset_n => count1[0].ACLR
reset_n => count1[1].ACLR
reset_n => count1[2].ACLR
reset_n => ML[0].ACLR
reset_n => ML[1].ACLR
reset_n => ML[2].ACLR
reset_n => ML[3].ACLR
reset_n => MH[0].ACLR
reset_n => MH[1].ACLR
reset_n => MH[2].ACLR
reset_n => MH[3].ACLR
reset_n => cn2.ACLR
reset_n => SL[0].ACLR
reset_n => SL[1].ACLR
reset_n => SL[2].ACLR
reset_n => SL[3].ACLR
reset_n => SH[0].ACLR
reset_n => SH[1].ACLR
reset_n => SH[2].ACLR
reset_n => SH[3].ACLR
reset_n => MSH[3].ACLR
reset_n => MSH[2].ACLR
reset_n => MSH[1].ACLR
reset_n => MSH[0].ACLR
reset_n => MSL[3].ACLR
reset_n => MSL[2].ACLR
reset_n => MSL[1].ACLR
reset_n => MSL[0].ACLR
reset_n => cn1.ACLR
dataout[0] <= dataout~1.DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= dataout~0.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
dataout[6] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
dataout[7] <= <VCC>
comout[0] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
comout[1] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
comout[2] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
comout[3] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
comout[4] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE
comout[5] <= Decoder0.DB_MAX_OUTPUT_PORT_TYPE