prev_cmp_clock.qmsg

用verilog实现的数字跑表

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 28 22:24:34 2009 " "Info: Processing started: Wed Jan 28 22:24:34 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/clock/clock.v " "Warning: Can't analyze file -- file F:/work/project/clock/clock.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.bdf" "" { Schematic "F:/work/project/clock/clock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdivisor.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clockdivisor.v" { { "Info" "ISGN_ENTITY_NAME" "1 clockdivisor " "Info: Found entity 1: clockdivisor" {  } { { "clockdivisor.v" "" { Text "F:/work/project/clock/clockdivisor.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "segmain0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file segmain0.v" { { "Info" "ISGN_ENTITY_NAME" "1 segmain0 " "Info: Found entity 1: segmain0" {  } { { "segmain0.v" "" { Text "F:/work/project/clock/segmain0.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "paobiao.v(22) " "Warning (10268): Verilog HDL information at paobiao.v(22): Always Construct contains both blocking and non-blocking assignments" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 22 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "paobiao.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file paobiao.v" { { "Info" "ISGN_ENTITY_NAME" "1 paobiao " "Info: Found entity 1: paobiao" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter.v" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Info: Found entity 1: shifter" {  } { { "shifter.v" "" { Text "F:/work/project/clock/shifter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file key.v" { { "Info" "ISGN_ENTITY_NAME" "1 key " "Info: Found entity 1: key" {  } { { "key.v" "" { Text "F:/work/project/clock/key.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "pause paobiao.v(27) " "Error (10137): Verilog HDL Procedural Assignment error at paobiao.v(27): object \"pause\" on left-hand side of assignment must have a variable data type" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 27 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0}
{ "Error" "EVRFX_VERI_ASSIGNMENT_TO_INPUT" "pause paobiao.v(27) " "Error (10231): Verilog HDL error at paobiao.v(27): value cannot be assigned to input \"pause\"" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 27 0 0 } }  } 0 10231 "Verilog HDL error at %2!s!: value cannot be assigned to input \"%1!s!\"" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/work/project/clock/clock.map.smsg " "Info: Generated suppressed messages file F:/work/project/clock/clock.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Allocated 136 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Wed Jan 28 22:24:35 2009 " "Error: Processing ended: Wed Jan 28 22:24:35 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 2 s 1  " "Error: Quartus II Full Compilation was unsuccessful. 2 errors, 1 warning" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}