prev_cmp_clock.map.qmsg

用verilog实现的数字跑表

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 30 14:18:34 2009 " "Info: Processing started: Fri Jan 30 14:18:34 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/work/project/clock/clock.v " "Warning: Can't analyze file -- file F:/work/project/clock/clock.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file clock.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.bdf" "" { Schematic "F:/work/project/clock/clock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clockdivisor.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clockdivisor.v" { { "Info" "ISGN_ENTITY_NAME" "1 clockdivisor " "Info: Found entity 1: clockdivisor" {  } { { "clockdivisor.v" "" { Text "F:/work/project/clock/clockdivisor.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "segmain0.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file segmain0.v" { { "Info" "ISGN_ENTITY_NAME" "1 segmain0 " "Info: Found entity 1: segmain0" {  } { { "segmain0.v" "" { Text "F:/work/project/clock/segmain0.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "paobiao.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file paobiao.v" { { "Info" "ISGN_ENTITY_NAME" "1 paobiao " "Info: Found entity 1: paobiao" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shifter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file shifter.v" { { "Info" "ISGN_ENTITY_NAME" "1 shifter " "Info: Found entity 1: shifter" {  } { { "shifter.v" "" { Text "F:/work/project/clock/shifter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file key.v" { { "Info" "ISGN_ENTITY_NAME" "1 key " "Info: Found entity 1: key" {  } { { "key.v" "" { Text "F:/work/project/clock/key.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "paobiao " "Info: Elaborating entity \"paobiao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 paobiao.v(35) " "Warning (10230): Verilog HDL assignment warning at paobiao.v(35): truncated value with size 32 to match size of target (4)" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 paobiao.v(38) " "Warning (10230): Verilog HDL assignment warning at paobiao.v(38): truncated value with size 32 to match size of target (4)" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 paobiao.v(53) " "Warning (10230): Verilog HDL assignment warning at paobiao.v(53): truncated value with size 32 to match size of target (4)" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 53 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 paobiao.v(56) " "Warning (10230): Verilog HDL assignment warning at paobiao.v(56): truncated value with size 32 to match size of target (4)" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 56 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 paobiao.v(66) " "Warning (10230): Verilog HDL assignment warning at paobiao.v(66): truncated value with size 32 to match size of target (4)" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 paobiao.v(68) " "Warning (10230): Verilog HDL assignment warning at paobiao.v(68): truncated value with size 32 to match size of target (4)" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 paobiao.v(77) " "Warning (10230): Verilog HDL assignment warning at paobiao.v(77): truncated value with size 32 to match size of target (3)" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "MSL paobiao.v(82) " "Warning (10235): Verilog HDL Always Construct warning at paobiao.v(82): variable \"MSL\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 82 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "MSH paobiao.v(83) " "Warning (10235): Verilog HDL Always Construct warning at paobiao.v(83): variable \"MSH\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 83 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "SL paobiao.v(84) " "Warning (10235): Verilog HDL Always Construct warning at paobiao.v(84): variable \"SL\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 84 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "SH paobiao.v(85) " "Warning (10235): Verilog HDL Always Construct warning at paobiao.v(85): variable \"SH\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 85 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "ML paobiao.v(86) " "Warning (10235): Verilog HDL Always Construct warning at paobiao.v(86): variable \"ML\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 86 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "MH paobiao.v(87) " "Warning (10235): Verilog HDL Always Construct warning at paobiao.v(87): variable \"MH\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 87 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "MSL paobiao.v(88) " "Warning (10235): Verilog HDL Always Construct warning at paobiao.v(88): variable \"MSL\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 88 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dataout\[7\] VCC " "Warning (13410): Pin \"dataout\[7\]\" stuck at VCC" {  } { { "paobiao.v" "" { Text "F:/work/project/clock/paobiao.v" 11 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "87 " "Info: Implemented 87 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "69 " "Info: Implemented 69 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 17 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Allocated 144 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 30 14:18:39 2009 " "Info: Processing ended: Fri Jan 30 14:18:39 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}