clockdivisor.v

用verilog实现的数字跑表

module clockdivisor(clk,reset_n,clk_odd,clk_odd1); 
/*count没必要放在端口中，这里只是为了仿真时观察*/
	input   clk,reset_n;
	output  clk_odd,clk_odd1;
	
	reg   clk_odd,clk_odd1;
	reg[31:0]   count;
	reg[31:0] count1;
	//parameter    N = 50000;
	                     
    always @ (posedge clk or negedge reset_n)
      if(! reset_n)
      
          begin        
            count <= 1'b0;
            clk_odd<= 1'b0;
          end
          
      else      
          if ( count <50000000/2-1)
            begin         
              count <= count + 1'b1;           
            end
          else
            begin       
              count <= 1'b0;
              clk_odd <= ~clk_odd;     
            end
  always @ (posedge clk or negedge reset_n)
      if(! reset_n)
      
          begin        
            count1 <= 1'b0;
            clk_odd1<= 1'b0;
          end
          
      else      
          if ( count1 <50000/2-1)
            begin         
              count1 <= count1 + 1'b1;           
            end
          else
            begin       
              count1 <= 1'b0;
              clk_odd1 <= ~clk_odd1;     
            end
 
endmodule