clock.tan.summary

用verilog实现的数字跑表

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.690 ns
From           : pause
To             : MSH[0]
From Clock     : --
To Clock       : clk_odd
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 22.254 ns
From           : ML[1]
To             : dataout[2]
From Clock     : clk_odd
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.617 ns
From           : pause
To             : MSL[2]
From Clock     : --
To Clock       : clk_odd
Failed Paths   : 0

Type           : Clock Setup: 'clk_odd'
Slack          : N/A
Required Time  : None
Actual Time    : 180.47 MHz ( period = 5.541 ns )
From           : SH[3]
To             : cn2
From Clock     : clk_odd
To Clock       : clk_odd
Failed Paths   : 0

Type           : Clock Setup: 'clk_odd10'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 340.02 MHz ( period = 2.941 ns )
From           : count1[0]
To             : count1[2]
From Clock     : clk_odd10
To Clock       : clk_odd10
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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