clock.fit.summary

来自「用verilog实现的数字跑表」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Fri Jan 30 14:18:54 2009
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : clock
Top-level Entity Name : paobiao
Family : Cyclone II
Device : EP2C20Q240C8
Timing Models : Final
Total logic elements : 69 / 18,752 ( < 1 % )
    Total combinational functions : 69 / 18,752 ( < 1 % )
    Dedicated logic registers : 29 / 18,752 ( < 1 % )
Total registers : 29
Total pins : 18 / 142 ( 13 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )