shifter.v.bak

用verilog实现的数字跑表

module shifter(data0,data1,data2,data3,data4,data5,com,seg_data);
input [3:0]data0,data1,data2,data3,data4,data5;
//input clk;
output [5:0] com;
output [7:0]seg_data;
reg [7:0]seg_data;
reg[3:0]data;
reg[5:0]com;
parameter k=20000;
always//@(posedge clk)
begin
//com=6'b111110;
#k data=data0;
//#k com=6'b111101;
#k data=data1;
//#k com=6'b111011;
#k data=data2;
//#k com=6'b110111;
#k data=data3;
//#k com=6'b101111;
#k data=data4;
//#k com=6'b011111;
#k data=data5;
end
always@(data)
begin
com=6'b111110;
#(2*k) com=6'b111101;
#(2*k) com=6'b111011;
#(2*k) com=6'b110111;
#(2*k) com=6'b101111;
#(2*k) com=6'b011111;
end
always @(data)
begin
case(data)
4'h0:seg_data=8'hc0;
4'h1:seg_data=8'hf9;
4'h2:seg_data=8'ha4;
4'h3:seg_data=8'hb0;
4'h4:seg_data=8'h99;
4'h5:seg_data=8'h92;
4'h6:seg_data=8'h82;
4'h7:seg_data=8'hf8;
4'h8:seg_data=8'h80;
4'h9:seg_data=8'h90;

default:seg_data=8'hc0;
endcase
end
endmodule