_info

《设计与验证VerilogHDL》源码实例 和 Verilog规范

m255
cModel Technology
dC:\prj\Example-4-3\sim
vram_basic
IedNQZgjT=b?C_B5F?N75d1
VlLdfG0K:]a1H7BjL``:I81
dC:\prj\Example-4-6\sim
w1136913897
FC:/prj/Example-4-6/sim/ram_basic.v
L0 1
OE;L;5.8b;17
r1
31
o-work work
vram_basic_tb
ISaI=2L`T[Cd4Jbl:AfF5:3
VnNoAUM;6]`^QTa0R4?<bX0
dC:\prj\Example-4-6\sim
w1136914118
FC:/prj/Example-4-6/sim/ram_basic_tb.v
L0 2
OE;L;5.8b;17
r1
31
o-work work