📄 ram_basic.srr
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#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Wed Mar 08 21:20:06 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"C:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"
@I::"C:\prj\Example-4-13\ram_basic\ram_basic.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module ram_basic
@N:"C:\prj\Example-4-13\ram_basic\ram_basic.v":1:7:1:15|Synthesizing module ram_basic
@N: CL134 :"C:\prj\Example-4-13\ram_basic\ram_basic.v":13:5:13:10|Found RAM RAM8x64, depth=64, width=8
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Mar 08 21:20:06 2006
###########################################################[
Version 8.1
Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May 9 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Reading Xilinx I/O pad type table from file <C:\eda\synplicity\fpga_81\lib/xilinx/x_io_tbl.txt>
Reading Xilinx Rocket I/O parameter type table from file <C:\eda\synplicity\fpga_81\lib/xilinx/gttype.txt>
@N: MT204 |Autoconstrain Mode is ON
RTL optimization done.
Clock Buffers:
Inserting Clock buffer for port clk, TNM=clk
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:0m:2s 0.00ns 3 / 8
2 0h:0m:2s 0.00ns 3 / 8
3 0h:0m:2s 0.00ns 3 / 8
------------------------------------------------------------
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Net buffering Report for view:work.ram_basic(verilog):
No nets needed buffering.
@N: FX164 |The option to pack flops in the IOB has not been specified
Writing Analyst data base C:\prj\Example-4-13\ram_basic\rev_2\ram_basic.srm
Writing EDIF Netlist and constraint files
Found clock ram_basic|clk with period 2.72ns
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Mar 08 21:20:10 2006
#
Top view: ram_basic
Requested Frequency: 368.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: -0.480
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------
ram_basic|clk 368.0 MHz 312.8 MHz 2.717 3.197 -0.480 inferred Autoconstr_clkgroup_0
========================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------------------
ram_basic|clk ram_basic|clk | 2.717 -0.480 | No paths - | No paths - | No paths -
=====================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: ram_basic|clk
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------
RAM8x64.I_1 ram_basic|clk RAM64X1S O RAM8x64[0] 2.284 -0.480
RAM8x64.I_2 ram_basic|clk RAM64X1S O RAM8x64[1] 2.284 -0.480
RAM8x64.I_5 ram_basic|clk RAM64X1S O RAM8x64[6] 2.284 -0.480
RAM8x64.I_6 ram_basic|clk RAM64X1S O RAM8x64[7] 2.284 -0.480
RAM8x64.I_9 ram_basic|clk RAM64X1S O RAM8x64[4] 2.284 -0.480
RAM8x64.I_10 ram_basic|clk RAM64X1S O RAM8x64[5] 2.284 -0.480
RAM8x64.I_13 ram_basic|clk RAM64X1S O RAM8x64[2] 2.284 -0.480
RAM8x64.I_14 ram_basic|clk RAM64X1S O RAM8x64[3] 2.284 -0.480
=========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------
mem_data[0] ram_basic|clk FDE D RAM8x64[0] 2.514 -0.480
mem_data[1] ram_basic|clk FDE D RAM8x64[1] 2.514 -0.480
mem_data[2] ram_basic|clk FDE D RAM8x64[2] 2.514 -0.480
mem_data[3] ram_basic|clk FDE D RAM8x64[3] 2.514 -0.480
mem_data[4] ram_basic|clk FDE D RAM8x64[4] 2.514 -0.480
mem_data[5] ram_basic|clk FDE D RAM8x64[5] 2.514 -0.480
mem_data[6] ram_basic|clk FDE D RAM8x64[6] 2.514 -0.480
mem_data[7] ram_basic|clk FDE D RAM8x64[7] 2.514 -0.480
=====================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 2.717
- Setup time: 0.203
= Required time: 2.514
- Propagation time: 2.994
= Slack (critical) : -0.480
Number of logic level(s): 0
Starting point: RAM8x64.I_1 / O
Ending point: mem_data[0] / D
The start point is clocked by ram_basic|clk [rising] on pin WCLK
The end point is clocked by ram_basic|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RAM8x64.I_1 RAM64X1S O Out 2.284 2.284 -
RAM8x64[0] Net - - 0.710 - 1
mem_data[0] FDE D In - 2.994 -
=================================================================================
Total path delay (propagation time + setup) of 3.197 is 2.487(77.8%) logic and 0.710(22.2%) route.
Path information for path number 2:
Requested Period: 2.717
- Setup time: 0.203
= Required time: 2.514
- Propagation time: 2.994
= Slack (critical) : -0.480
Number of logic level(s): 0
Starting point: RAM8x64.I_2 / O
Ending point: mem_data[1] / D
The start point is clocked by ram_basic|clk [rising] on pin WCLK
The end point is clocked by ram_basic|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RAM8x64.I_2 RAM64X1S O Out 2.284 2.284 -
RAM8x64[1] Net - - 0.710 - 1
mem_data[1] FDE D In - 2.994 -
=================================================================================
Total path delay (propagation time + setup) of 3.197 is 2.487(77.8%) logic and 0.710(22.2%) route.
Path information for path number 3:
Requested Period: 2.717
- Setup time: 0.203
= Required time: 2.514
- Propagation time: 2.994
= Slack (critical) : -0.480
Number of logic level(s): 0
Starting point: RAM8x64.I_5 / O
Ending point: mem_data[6] / D
The start point is clocked by ram_basic|clk [rising] on pin WCLK
The end point is clocked by ram_basic|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RAM8x64.I_5 RAM64X1S O Out 2.284 2.284 -
RAM8x64[6] Net - - 0.710 - 1
mem_data[6] FDE D In - 2.994 -
=================================================================================
Total path delay (propagation time + setup) of 3.197 is 2.487(77.8%) logic and 0.710(22.2%) route.
Path information for path number 4:
Requested Period: 2.717
- Setup time: 0.203
= Required time: 2.514
- Propagation time: 2.994
= Slack (critical) : -0.480
Number of logic level(s): 0
Starting point: RAM8x64.I_6 / O
Ending point: mem_data[7] / D
The start point is clocked by ram_basic|clk [rising] on pin WCLK
The end point is clocked by ram_basic|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RAM8x64.I_6 RAM64X1S O Out 2.284 2.284 -
RAM8x64[7] Net - - 0.710 - 1
mem_data[7] FDE D In - 2.994 -
=================================================================================
Total path delay (propagation time + setup) of 3.197 is 2.487(77.8%) logic and 0.710(22.2%) route.
Path information for path number 5:
Requested Period: 2.717
- Setup time: 0.203
= Required time: 2.514
- Propagation time: 2.994
= Slack (critical) : -0.480
Number of logic level(s): 0
Starting point: RAM8x64.I_9 / O
Ending point: mem_data[4] / D
The start point is clocked by ram_basic|clk [rising] on pin WCLK
The end point is clocked by ram_basic|clk [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RAM8x64.I_9 RAM64X1S O Out 2.284 2.284 -
RAM8x64[4] Net - - 0.710 - 1
mem_data[4] FDE D In - 2.994 -
=================================================================================
Total path delay (propagation time + setup) of 3.197 is 2.487(77.8%) logic and 0.710(22.2%) route.
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report for ram_basic
Mapping to part: xc3s50tq144-4
Cell usage:
FDE 8 uses
RAM64X1S 8 uses
LUT2 3 uses
I/O primitives: 25
IBUF 17 uses
OBUF 8 uses
BUFGP 1 use
I/O Register bits: 0
Register bits not including I/Os: 8 (0%)
RAM/ROM usage summary
Single Port Rams (RAM64X1S): 8
Global Clock Buffers: 1 of 8 (12%)
Mapping Summary:
Total LUTs: 35 (2%)
Mapper successful!
Process took 0h:0m:2s realtime, 0h:0m:2s cputime
###########################################################]
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