ram_basic.edf

《设计与验证VerilogHDL》源码实例 和 Verilog规范

(edif ram_basic
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2006 3 8 21 20 9)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "8.1.0, Build 540R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell RAM16X1S (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
           (port A3 (direction INPUT))
           (port D (direction INPUT))
           (port WCLK (direction INPUT)
 )
           (port WE (direction INPUT))
         )
       )
    )
    (cell RAM32X1S (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
           (port A3 (direction INPUT))
           (port A4 (direction INPUT))
           (port D (direction INPUT))
           (port WCLK (direction INPUT)
 )
           (port WE (direction INPUT))
         )
       )
    )
    (cell RAM64X1S (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
           (port A3 (direction INPUT))
           (port A4 (direction INPUT))
           (port A5 (direction INPUT))
           (port D (direction INPUT))
           (port WCLK (direction INPUT)
 )
           (port WE (direction INPUT))
         )
       )
    )
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell LUT2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell BUFGP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CE (direction INPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell ram_basic (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port (array (rename addr "addr[5:0]") 6) (direction INPUT))
           (port (array (rename data_in "data_in[7:0]") 8) (direction INPUT))
           (port (array (rename data_out "data_out[7:0]") 8) (direction OUTPUT))
           (port clk (direction INPUT)
 )
           (port CS (direction INPUT)
 )
           (port WR (direction INPUT)
 )
           (port en (direction INPUT)
 )
         )
         (contents
          (instance (rename mem_data_0 "mem_data[0]") (viewRef PRIM (cellRef FDE (libraryRef UNILIB)))
          )
          (instance (rename mem_data_1 "mem_data[1]") (viewRef PRIM (cellRef FDE (libraryRef UNILIB)))
          )
          (instance (rename mem_data_2 "mem_data[2]") (viewRef PRIM (cellRef FDE (libraryRef UNILIB)))
          )
          (instance (rename mem_data_3 "mem_data[3]") (viewRef PRIM (cellRef FDE (libraryRef UNILIB)))
          )
          (instance (rename mem_data_4 "mem_data[4]") (viewRef PRIM (cellRef FDE (libraryRef UNILIB)))
          )
          (instance (rename mem_data_5 "mem_data[5]") (viewRef PRIM (cellRef FDE (libraryRef UNILIB)))
          )
          (instance (rename mem_data_6 "mem_data[6]") (viewRef PRIM (cellRef FDE (libraryRef UNILIB)))
          )
          (instance (rename mem_data_7 "mem_data[7]") (viewRef PRIM (cellRef FDE (libraryRef UNILIB)))
          )
          (instance mem_data5_0_a2 (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "2"))
          )
          (instance mem_data4_0_a2 (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "8"))
          )
          (instance (rename data_out_1_7 "data_out_1[7]") (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance clk_ibuf (viewRef PRIM (cellRef BUFGP (libraryRef VIRTEX)))
          )
          (instance (rename data_out_obuf_7 "data_out_obuf[7]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_out_obuf_6 "data_out_obuf[6]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_out_obuf_5 "data_out_obuf[5]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_out_obuf_4 "data_out_obuf[4]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_out_obuf_3 "data_out_obuf[3]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_out_obuf_2 "data_out_obuf[2]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_out_obuf_1 "data_out_obuf[1]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_out_obuf_0 "data_out_obuf[0]") (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance en_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_in_ibuf_7 "data_in_ibuf[7]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_in_ibuf_6 "data_in_ibuf[6]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_in_ibuf_5 "data_in_ibuf[5]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_in_ibuf_4 "data_in_ibuf[4]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_in_ibuf_3 "data_in_ibuf[3]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_in_ibuf_2 "data_in_ibuf[2]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_in_ibuf_1 "data_in_ibuf[1]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename data_in_ibuf_0 "data_in_ibuf[0]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename addr_ibuf_5 "addr_ibuf[5]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename addr_ibuf_4 "addr_ibuf[4]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename addr_ibuf_3 "addr_ibuf[3]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename addr_ibuf_2 "addr_ibuf[2]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename addr_ibuf_1 "addr_ibuf[1]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename addr_ibuf_0 "addr_ibuf[0]") (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance WR_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance CS_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (instance (rename RAM8x64_I_14 "RAM8x64.I_14") (viewRef PRIM (cellRef RAM64X1S (libraryRef VIRTEX)))
           (property skip_one_hierarchy (integer 1))
          )
          (instance (rename RAM8x64_I_13 "RAM8x64.I_13") (viewRef PRIM (cellRef RAM64X1S (libraryRef VIRTEX)))
           (property skip_one_hierarchy (integer 1))
          )
          (instance (rename RAM8x64_I_10 "RAM8x64.I_10") (viewRef PRIM (cellRef RAM64X1S (libraryRef VIRTEX)))
           (property skip_one_hierarchy (integer 1))
          )
          (instance (rename RAM8x64_I_9 "RAM8x64.I_9") (viewRef PRIM (cellRef RAM64X1S (libraryRef VIRTEX)))
           (property skip_one_hierarchy (integer 1))
          )
          (instance (rename RAM8x64_I_6 "RAM8x64.I_6") (viewRef PRIM (cellRef RAM64X1S (libraryRef VIRTEX)))
           (property skip_one_hierarchy (integer 1))
          )
          (instance (rename RAM8x64_I_5 "RAM8x64.I_5") (viewRef PRIM (cellRef RAM64X1S (libraryRef VIRTEX)))
           (property skip_one_hierarchy (integer 1))
          )
          (instance (rename RAM8x64_I_2 "RAM8x64.I_2") (viewRef PRIM (cellRef RAM64X1S (libraryRef VIRTEX)))
           (property skip_one_hierarchy (integer 1))
          )
          (instance (rename RAM8x64_I_1 "RAM8x64.I_1") (viewRef PRIM (cellRef RAM64X1S (libraryRef VIRTEX)))
           (property skip_one_hierarchy (integer 1))
          )
          (net clk (joined
           (portRef clk)
           (portRef I (instanceRef clk_ibuf))
          ))
          (net (rename cs "CS") (joined
           (portRef CS)
           (portRef I (instanceRef CS_ibuf))
          ))
          (net (rename wr "WR") (joined
           (portRef WR)
           (portRef I (instanceRef WR_ibuf))
          ))
          (net (rename addr_0 "addr[0]") (joined
           (portRef (member addr 5))
           (portRef I (instanceRef addr_ibuf_0))
          ))
          (net (rename addr_1 "addr[1]") (joined
           (portRef (member addr 4))
           (portRef I (instanceRef addr_ibuf_1))
          ))
          (net (rename addr_2 "addr[2]") (joined
           (portRef (member addr 3))
           (portRef I (instanceRef addr_ibuf_2))
          ))
          (net (rename addr_3 "addr[3]") (joined
           (portRef (member addr 2))
           (portRef I (instanceRef addr_ibuf_3))
          ))
          (net (rename addr_4 "addr[4]") (joined
           (portRef (member addr 1))
           (portRef I (instanceRef addr_ibuf_4))
          ))
          (net (rename addr_5 "addr[5]") (joined
           (portRef (member addr 0))
           (portRef I (instanceRef addr_ibuf_5))
          ))
          (net (rename data_in_0 "data_in[0]") (joined
           (portRef (member data_in 7))
           (portRef I (instanceRef data_in_ibuf_0))
          ))
          (net (rename data_in_1 "data_in[1]") (joined
           (portRef (member data_in 6))
           (portRef I (instanceRef data_in_ibuf_1))
          ))
          (net (rename data_in_2 "data_in[2]") (joined
           (portRef (member data_in 5))
           (portRef I (instanceRef data_in_ibuf_2))
          ))
          (net (rename data_in_3 "data_in[3]") (joined
           (portRef (member data_in 4))
           (portRef I (instanceRef data_in_ibuf_3))
          ))