un_shannon.msg

《设计与验证VerilogHDL》源码实例 和 Verilog规范

@TM:1141812573
@N:  :"":0:0:0:-1|Only System clock will be Autoconstrained
@TM:1141813814
@N: FA174 :"":0:0:0:-1|The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
@TM:1141812573
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1141813253
@N:  :"c:\prj\chapter5\example-5-8\source\shannon_fast.v":1:7:1:18|Synthesizing module shannon_fast