latch.msg

《设计与验证VerilogHDL》源码实例 和 Verilog规范

@TM:1136213275
@N:  :"":0:0:0:-1|Only System clock will be Autoconstrained
@N: FX164 :"":0:0:0:-1|The option to pack flops in the IOB has not been specified 
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1136213272
@N:  :"c:\prj\example-5-2\latch.v":1:7:1:11|Synthesizing module latch
@TM:1136213275
@W:  :"c:\prj\example-5-2\latch.v":3:6:3:11|M
@TM:1136213272
@W: CL118 :"c:\prj\example-5-2\latch.v":10:4:10:5|M