case1_area.rep

《设计与验证VerilogHDL》源码实例 和 Verilog规范

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Device Utilization for LFEC20E-3F672CES
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Resource                Used    Avail   Utilization
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IOs                     9       400       2.25%
LUTs                    3       19700     0.02%
PFUs                    1       4925      0.02%
Flipflops               0       19700     0.00%
Block RAMs              0       46        0.00%

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Library: work    Cell: case1    View: INTERFACE

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  Cell       Library  References     Total Area

 IB          lattice_ec     8 x
 OB          lattice_ec     1 x
 ORCALUT3    lattice_ec     1 x      1      1 LUTs
 ORCALUT4    lattice_ec     2 x      1      2 LUTs

 Number of ports :                       9
 Number of nets :                       20
 Number of instances :                  12
 Number of references to this view :     0

Total accumulated area : 
 Number of LUTs :                        3
 Number of gates :                       0
 Number of accumulated instances :      12