_info

《设计与验证VerilogHDL》源码实例 和 Verilog规范

m255
cModel Technology
dC:\prj\Example-4-2\sim
vdecode_cmb
IVW1e0L6YL@SKb<MAlmU]R1
V;fm[ilGH92CcIo`Ri<Vdh2
dC:\prj\Example-4-3\sim
w1136834122
FC:/prj/Example-4-3/sim/decode_cmb.v
L0 1
OE;L;5.8b;17
r1
31
o-work work
vdecode_cmb2
Ib@>A=<jggTO]J:8J3PIJl3
VHeBSFG@VZezn6Z=nZe?_k1
dC:\prj\Example-4-3\sim
w1136834124
FC:/prj/Example-4-3/sim/decode_cmb2.v
L0 1
OE;L;5.8b;17
r1
31
o-work work
vdecode_cmb_tb
IZOia2_CNPj6BMA>J>X_T>3
Vihe;k_a@McHMi[`W[TznO1
dC:\prj\Example-4-3\sim
w1136834492
FC:/prj/Example-4-3/sim/decode_cmb_tb.v
L0 2
OE;L;5.8b;17
r1
31
o-work work