decode_cmb2.msg

《设计与验证VerilogHDL》源码实例 和 Verilog规范

@TM:1136833017
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1136833016
@N:  :"c:\prj\example-4-3\decode_cmb.v":1:7:1:16|Synthesizing module decode_cmb
@W:  :"c:\prj\example-4-3\decode_cmb.v":3:18:3:21|M