clk_div_phase.ncf

《设计与验证VerilogHDL》源码实例 和 Verilog规范

#
# Constraints generated by Synplify Pro 8.1.0, Build 540R
#

# Period Constraints

#Begin clock constraints
NET "clk_200M" TNM_NET = "clk_200M"; 
TIMESPEC "TS_clk_200M" = PERIOD "clk_200M" 1.879 ns HIGH 50.00%; 
#End clock constraints

# Output Constraints
# Input Constraints

# I/O Registers Packing Constraints
INST "cnt_rep0_i[2]" IOB=FALSE;
INST "cnt_rep0_i[1]" IOB=FALSE;
INST "cnt_rep0_i[0]" IOB=FALSE;

# Location Constraints

# End of generated constraints