clk_div_phase.msg

《设计与验证VerilogHDL》源码实例 和 Verilog规范

@TM:1136917247
@N: FX164 :"":0:0:0:-1|The option to pack flops in the IOB has not been specified 
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1136917246
@N:  :"c:\prj\example-4-7\clk_div_phase\clk_div_phase.v":1:7:1:19|Synthesizing module clk_div_phase
@W:  :"c:\prj\example-4-7\clk_div_phase\clk_div_phase.v":5:32:5:37|M
@W: CL157 :"c:\prj\example-4-7\clk_div_phase\clk_div_phase.v":5:32:5:37|M
@TM:1136917247
@W: MO111 :"c:\prj\example-4-7\clk_div_phase\clk_div_phase.v":5:32:5:37|M
@TM:1136917246
@W: CL170 :"c:\prj\example-4-7\clk_div_phase\clk_div_phase.v":10:0:10:5|M