📄 syn_rst.srr
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#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Wed Jan 11 15:52:38 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"C:\eda\synplicity\fpga_81\lib\lucent\xp.v"
@I::"C:\prj\Example-4-9\syn_rst\syn_rst.v"
Verilog syntax check successful!
File C:\prj\Example-4-9\syn_rst\syn_rst.v changed - recompiling
Selecting top level module syn_rst
@N:"C:\prj\Example-4-9\syn_rst\syn_rst.v":1:7:1:13|Synthesizing module syn_rst
@N: CG179 :"C:\prj\Example-4-9\syn_rst\syn_rst.v":20:20:20:23|Removing redundant assignment
@W: CL189 :"C:\prj\Example-4-9\syn_rst\syn_rst.v":9:0:9:5|Register bit cnt1[2] is always 0, optimizing ...
@W: CL189 :"C:\prj\Example-4-9\syn_rst\syn_rst.v":9:0:9:5|Register bit cnt1[3] is always 0, optimizing ...
@W: CL189 :"C:\prj\Example-4-9\syn_rst\syn_rst.v":9:0:9:5|Register bit cnt1[4] is always 0, optimizing ...
@W: CL171 :"C:\prj\Example-4-9\syn_rst\syn_rst.v":9:0:9:5|Pruning Register bit <4> of cnt1[4:0]
@W: CL171 :"C:\prj\Example-4-9\syn_rst\syn_rst.v":9:0:9:5|Pruning Register bit <3> of cnt1[4:0]
@W: CL171 :"C:\prj\Example-4-9\syn_rst\syn_rst.v":9:0:9:5|Pruning Register bit <2> of cnt1[4:0]
@W: CL171 :"C:\prj\Example-4-9\syn_rst\syn_rst.v":9:0:9:5|Pruning Register bit <4> of cnt2[4:0]
@W: CL171 :"C:\prj\Example-4-9\syn_rst\syn_rst.v":9:0:9:5|Pruning Register bit <3> of cnt2[4:0]
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 11 15:52:38 2006
###########################################################[
Version 8.1
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Setting fanout limit to 100
Starting Generic Flow
@N: MT204 |Autoconstrain Mode is ON
@W: BN132 :|Removing instance un3_cnt2_1.N_13_i, because it is equivalent to instance un3_cnt2_1.N_13_i_rep1
@W: BN132 :"c:\prj\example-4-9\syn_rst\syn_rst.v":9:0:9:5|Removing instance cnt1_1_1_.Q, because it is equivalent to instance cnt1_1_fast_1_.Q
---------------------------------------
Resource Usage Report
Part: lfxp10c-4
Register bits: 5 of 9728 (0%)
I/O cells: 12
Details:
FD1S3AX: 5
IB: 2
OB: 10
ORCALUT4: 5
VHI: 1
VLO: 1
Found clock syn_rst|clk with period 2.69ns
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jan 11 15:52:40 2006
#
Top view: syn_rst
Requested Frequency: 371.2 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: -0.475
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------------
syn_rst|clk 371.2 MHz 315.5 MHz 2.694 3.169 -0.475 inferred Autoconstr_clkgroup_0
========================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-----------------------------------------------------------------------------------------------------------------
syn_rst|clk syn_rst|clk | 2.694 -0.475 | No paths - | No paths - | No paths -
=================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: syn_rst|clk
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------
cnt1_1_0_.Q syn_rst|clk FD1S3AX Q cnt1_c[0] 1.756 -0.475
cnt1_1_fast_1_.Q syn_rst|clk FD1S3AX Q cnt1_c[1] 1.627 -0.347
=========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------
cnt1_1_0_.Q syn_rst|clk FD1S3AX D N_20 2.416 -0.475
cnt1_1_fast_1_.Q syn_rst|clk FD1S3AX D N_21 2.416 -0.475
cnt2_1_0_.Q syn_rst|clk FD1S3AX D N_22 2.416 -0.475
cnt2_1_1_.Q syn_rst|clk FD1S3AX D N_23 2.416 -0.475
cnt2_1_2_.Q syn_rst|clk FD1S3AX D N_24 2.416 -0.475
=====================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 2.694
- Setup time: 0.278
= Required time: 2.416
- Propagation time: 2.891
= Slack (critical) : -0.475
Number of logic level(s): 1
Starting point: cnt1_1_0_.Q / Q
Ending point: cnt1_1_0_.Q / D
The start point is clocked by syn_rst|clk [rising] on pin CK
The end point is clocked by syn_rst|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
cnt1_1_0_.Q FD1S3AX Q Out 1.756 1.756 -
cnt1_c[0] Net - - - - 6
cnt1_1_0_.Q_0_0_a2 ORCALUT4 A In 0.000 1.756 -
cnt1_1_0_.Q_0_0_a2 ORCALUT4 Z Out 1.136 2.891 -
N_20 Net - - - - 1
cnt1_1_0_.Q FD1S3AX D In 0.000 2.891 -
=====================================================================================
Path information for path number 2:
Requested Period: 2.694
- Setup time: 0.278
= Required time: 2.416
- Propagation time: 2.891
= Slack (critical) : -0.475
Number of logic level(s): 1
Starting point: cnt1_1_0_.Q / Q
Ending point: cnt2_1_2_.Q / D
The start point is clocked by syn_rst|clk [rising] on pin CK
The end point is clocked by syn_rst|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
cnt1_1_0_.Q FD1S3AX Q Out 1.756 1.756 -
cnt1_c[0] Net - - - - 6
cnt2_1_2_.Q_0_0_a2 ORCALUT4 C In 0.000 1.756 -
cnt2_1_2_.Q_0_0_a2 ORCALUT4 Z Out 1.136 2.891 -
N_24 Net - - - - 1
cnt2_1_2_.Q FD1S3AX D In 0.000 2.891 -
=====================================================================================
Path information for path number 3:
Requested Period: 2.694
- Setup time: 0.278
= Required time: 2.416
- Propagation time: 2.891
= Slack (critical) : -0.475
Number of logic level(s): 1
Starting point: cnt1_1_0_.Q / Q
Ending point: cnt2_1_1_.Q / D
The start point is clocked by syn_rst|clk [rising] on pin CK
The end point is clocked by syn_rst|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
cnt1_1_0_.Q FD1S3AX Q Out 1.756 1.756 -
cnt1_c[0] Net - - - - 6
cnt2_1_1_.Q_0_0_a2 ORCALUT4 C In 0.000 1.756 -
cnt2_1_1_.Q_0_0_a2 ORCALUT4 Z Out 1.136 2.891 -
N_23 Net - - - - 1
cnt2_1_1_.Q FD1S3AX D In 0.000 2.891 -
=====================================================================================
Path information for path number 4:
Requested Period: 2.694
- Setup time: 0.278
= Required time: 2.416
- Propagation time: 2.891
= Slack (critical) : -0.475
Number of logic level(s): 1
Starting point: cnt1_1_0_.Q / Q
Ending point: cnt1_1_fast_1_.Q / D
The start point is clocked by syn_rst|clk [rising] on pin CK
The end point is clocked by syn_rst|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
cnt1_1_0_.Q FD1S3AX Q Out 1.756 1.756 -
cnt1_c[0] Net - - - - 6
cnt1_1_1_.Q_0_0_a2 ORCALUT4 C In 0.000 1.756 -
cnt1_1_1_.Q_0_0_a2 ORCALUT4 Z Out 1.136 2.891 -
N_21 Net - - - - 1
cnt1_1_fast_1_.Q FD1S3AX D In 0.000 2.891 -
=====================================================================================
Path information for path number 5:
Requested Period: 2.694
- Setup time: 0.278
= Required time: 2.416
- Propagation time: 2.891
= Slack (critical) : -0.475
Number of logic level(s): 1
Starting point: cnt1_1_0_.Q / Q
Ending point: cnt2_1_0_.Q / D
The start point is clocked by syn_rst|clk [rising] on pin CK
The end point is clocked by syn_rst|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------
cnt1_1_0_.Q FD1S3AX Q Out 1.756 1.756 -
cnt1_c[0] Net - - - - 6
cnt2_1_0_.Q_0_0_a2 ORCALUT4 B In 0.000 1.756 -
cnt2_1_0_.Q_0_0_a2 ORCALUT4 Z Out 1.136 2.891 -
N_22 Net - - - - 1
cnt2_1_0_.Q FD1S3AX D In 0.000 2.891 -
=====================================================================================
##### END OF TIMING REPORT #####]
Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]
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