📄 state2_default.srr
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#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Fri Dec 16 16:56:08 2005
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"C:\eda\synplicity\fpga_81\lib\lucent\ec.v"
@I::"C:\prj\FSM_abc\state_default\state2_default.v"
Verilog syntax check successful!
Selecting top level module state2_default
@N:"C:\prj\FSM_abc\state_default\state2_default.v":2:7:2:20|Synthesizing module state2_default
@N: CL201 :"C:\prj\FSM_abc\state_default\state2_default.v":23:0:23:5|Trying to extract state machine for register CS
Extracted state machine for register CS
State machine has 4 reachable states with original encodings of:
000
001
010
100
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Dec 16 16:56:08 2005
###########################################################[
Version 8.1
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Setting fanout limit to 100
Starting Generic Flow
@N: MT204 |Autoconstrain Mode is ON
---------------------------------------
Resource Usage Report
Part: lfec1e-3
Register bits: 2 of 1536 (0%)
I/O cells: 7
Details:
FD1S3AX: 2
GSR: 1
IB: 4
OB: 3
ORCALUT4: 5
VHI: 1
VLO: 1
Found clock state2_default|clk with period 2.75ns
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Dec 16 16:56:10 2005
#
Top view: state2_default
Requested Frequency: 364.2 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: -0.484
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------------
state2_default|clk 364.2 MHz 309.6 MHz 2.745 3.230 -0.484 inferred Autoconstr_clkgroup_0
============================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------
state2_default|clk state2_default|clk | 2.746 -0.485 | No paths - | No paths - | No paths -
===============================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: state2_default|clk
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
CS_0_.Q state2_default|clk FD1S3AX Q o1_9 1.690 -0.484
CS_1_.Q state2_default|clk FD1S3AX Q o2_9 1.690 -0.484
===================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------
CS_0_.Q state2_default|clk FD1S3AX D N_6_i 2.422 -0.484
CS_1_.Q state2_default|clk FD1S3AX D N_35_i 2.422 -0.484
======================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 2.745
- Setup time: 0.324
= Required time: 2.422
- Propagation time: 2.906
= Slack (critical) : -0.485
Number of logic level(s): 1
Starting point: CS_0_.Q / Q
Ending point: CS_0_.Q / D
The start point is clocked by state2_default|clk [rising] on pin CK
The end point is clocked by state2_default|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
CS_0_.Q FD1S3AX Q Out 1.690 1.690 -
o1_9 Net - - - - 4
N_6_i ORCALUT4 C In 0.000 1.690 -
N_6_i ORCALUT4 Z Out 1.216 2.906 -
N_6_i Net - - - - 1
CS_0_.Q FD1S3AX D In 0.000 2.906 -
=================================================================================
Path information for path number 2:
Requested Period: 2.745
- Setup time: 0.324
= Required time: 2.422
- Propagation time: 2.906
= Slack (critical) : -0.485
Number of logic level(s): 1
Starting point: CS_1_.Q / Q
Ending point: CS_0_.Q / D
The start point is clocked by state2_default|clk [rising] on pin CK
The end point is clocked by state2_default|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
CS_1_.Q FD1S3AX Q Out 1.690 1.690 -
o2_9 Net - - - - 4
N_6_i ORCALUT4 D In 0.000 1.690 -
N_6_i ORCALUT4 Z Out 1.216 2.906 -
N_6_i Net - - - - 1
CS_0_.Q FD1S3AX D In 0.000 2.906 -
=================================================================================
Path information for path number 3:
Requested Period: 2.745
- Setup time: 0.324
= Required time: 2.422
- Propagation time: 2.906
= Slack (critical) : -0.485
Number of logic level(s): 1
Starting point: CS_0_.Q / Q
Ending point: CS_1_.Q / D
The start point is clocked by state2_default|clk [rising] on pin CK
The end point is clocked by state2_default|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
CS_0_.Q FD1S3AX Q Out 1.690 1.690 -
o1_9 Net - - - - 4
N_35_i ORCALUT4 C In 0.000 1.690 -
N_35_i ORCALUT4 Z Out 1.216 2.906 -
N_35_i Net - - - - 1
CS_1_.Q FD1S3AX D In 0.000 2.906 -
=================================================================================
Path information for path number 4:
Requested Period: 2.745
- Setup time: 0.324
= Required time: 2.422
- Propagation time: 2.906
= Slack (critical) : -0.485
Number of logic level(s): 1
Starting point: CS_1_.Q / Q
Ending point: CS_1_.Q / D
The start point is clocked by state2_default|clk [rising] on pin CK
The end point is clocked by state2_default|clk [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
CS_1_.Q FD1S3AX Q Out 1.690 1.690 -
o2_9 Net - - - - 4
N_35_i ORCALUT4 D In 0.000 1.690 -
N_35_i ORCALUT4 Z Out 1.216 2.906 -
N_35_i Net - - - - 1
CS_1_.Q FD1S3AX D In 0.000 2.906 -
=================================================================================
##### END OF TIMING REPORT #####]
Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]
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