state1.prd

来自「《设计与验证VerilogHDL》源码实例 和 Verilog规范」· PRD 代码 · 共 14 行

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\FSM_abc\state1\state1.prd
#-- Written on Fri Dec 16 14:50:01 2005

#
### Watch Implementation type ###
#
watch_impl -all
#
### Watch Implementation properties ###
#
watch_prop -clear {  state1|clk - Estimated Frequency }