📄 top.srr
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#Program: Synplify Pro 8.1
#OS: Windows_NT
$ Start of Compile
#Thu Mar 09 01:49:24 2006
Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
@I::"C:\eda\synplicity\fpga_81\lib\lucent\ec.v"
@I::"C:\prj\Example-4-21\syn_wr\decode.v"
@I::"C:\prj\Example-4-21\syn_wr\read_reg.v"
@I::"C:\prj\Example-4-21\syn_wr\write_reg.v"
@I::"C:\prj\Example-4-21\syn_wr\top.v"
Verilog syntax check successful!
File C:\prj\Example-4-21\syn_wr\decode.v changed - recompiling
Selecting top level module top
@N:"C:\prj\Example-4-21\syn_wr\decode.v":3:7:3:12|Synthesizing module decode
@W: CL118 :"C:\prj\Example-4-21\syn_wr\decode.v":17:2:17:3|Latch generated from always block for signal CS_reg3, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:\prj\Example-4-21\syn_wr\decode.v":17:2:17:3|Latch generated from always block for signal CS_reg2, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:\prj\Example-4-21\syn_wr\decode.v":17:2:17:3|Latch generated from always block for signal CS_reg1, probably caused by a missing assignment in an if or case stmt
@N:"C:\prj\Example-4-21\syn_wr\write_reg.v":2:7:2:15|Synthesizing module write_reg
@N: CG179 :"C:\prj\Example-4-21\syn_wr\write_reg.v":29:29:29:32|Removing redundant assignment
@N: CG179 :"C:\prj\Example-4-21\syn_wr\write_reg.v":30:29:30:32|Removing redundant assignment
@N: CG179 :"C:\prj\Example-4-21\syn_wr\write_reg.v":31:29:31:32|Removing redundant assignment
@N:"C:\prj\Example-4-21\syn_wr\read_reg.v":2:7:2:14|Synthesizing module read_reg
@N:"C:\prj\Example-4-21\syn_wr\top.v":1:7:1:9|Synthesizing module top
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Mar 09 01:49:24 2006
###########################################################[
Version 8.1
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved
Setting fanout limit to 100
Starting Generic Flow
Automatic dissolve at startup in view:work.top(verilog) of read_reg_u1(read_reg)
Automatic dissolve at startup in view:work.top(verilog) of decode_u1(decode)
Warning: Forcing use of GSR for flip-flops and
latches that do not specify sets or resets
work.top(verilog)-decode_u1.CS_reg1.Q
work.top(verilog)-decode_u1.CS_reg2.Q
work.top(verilog)-decode_u1.CS_reg3.Q
---------------------------------------
Resource Usage Report
Part: lfec1e-3
Register bits: 32 of 1536 (2%)
Latch bits: 3
I/O cells: 21
Details:
BB: 8
FD1P3AX: 32
FD1S1A: 3
GSR: 1
IB: 13
INV: 1
ORCALUT4: 34
VHI: 1
VLO: 1
Found clock top|clk_cpu with period 1000.00ns
Found clock top|CS_ with period 1000.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Thu Mar 09 01:49:27 2006
#
Top view: top
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: 495.123
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-----------------------------------------------------------------------------------------------------------------------
top|CS_ 1.0 MHz 102.5 MHz 1000.000 9.754 495.123 inferred Inferred_clkgroup_0
top|clk_cpu 1.0 MHz 102.5 MHz 1000.000 9.754 995.849 inferred Inferred_clkgroup_0
=======================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------------
top|CS_ top|CS_ | No paths - | 1000.000 996.320 | No paths - | No paths -
top|CS_ top|clk_cpu | No paths - | No paths - | No paths - | 500.000 495.123
top|clk_cpu top|clk_cpu | 1000.000 995.849 | No paths - | No paths - | No paths -
======================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: top|CS_
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q top|CS_ FD1S1A Q CS_reg2 2.122 495.123
decode_u1.CS_reg1.Q top|CS_ FD1S1A Q CS_reg1 2.140 496.320
decode_u1.CS_reg3.Q top|CS_ FD1S1A Q CS_reg3 1.653 497.657
========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------
decode_u1.CS_reg1.Q top|CS_ FD1S1A D decode_u1.CS_reg1_1 999.676 996.320
decode_u1.CS_reg2.Q top|CS_ FD1S1A D decode_u1.CS_reg2_1 999.676 996.339
decode_u1.CS_reg3.Q top|CS_ FD1S1A D decode_u1.CS_reg3_1 999.676 996.808
=====================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 500.000
- Setup time: 0.324
= Required time: 499.676
- Propagation time: 4.553
= Slack (critical) : 495.123
Number of logic level(s): 2
Starting point: decode_u1.CS_reg2.Q / Q
Ending point: read_reg_u1.data_out_0_.Q / D
The start point is clocked by top|CS_ [falling] on pin CK
The end point is clocked by top|clk_cpu [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q FD1S1A Q Out 2.122 2.122 -
CS_reg2 Net - - - - 12
read_reg_u1.data_out_8_0[0] ORCALUT4 A In 0.000 2.122 -
read_reg_u1.data_out_8_0[0] ORCALUT4 Z Out 1.216 3.337 -
read_reg_u1.data_out_8_0[0] Net - - - - 1
read_reg_u1.data_out_8[0] ORCALUT4 B In 0.000 3.337 -
read_reg_u1.data_out_8[0] ORCALUT4 Z Out 1.216 4.553 -
read_reg_u1.data_out_8[0] Net - - - - 1
read_reg_u1.data_out_0_.Q FD1P3AX D In 0.000 4.553 -
==============================================================================================
====================================
Detailed Report for Clock: top|clk_cpu
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------
write_reg_u1.reg2_0_.Q top|clk_cpu FD1P3AX Q reg2[0] 1.396 995.849
write_reg_u1.reg2_1_.Q top|clk_cpu FD1P3AX Q reg2[1] 1.396 995.849
write_reg_u1.reg2_2_.Q top|clk_cpu FD1P3AX Q reg2[2] 1.396 995.849
write_reg_u1.reg2_3_.Q top|clk_cpu FD1P3AX Q reg2[3] 1.396 995.849
write_reg_u1.reg2_4_.Q top|clk_cpu FD1P3AX Q reg2[4] 1.396 995.849
write_reg_u1.reg2_5_.Q top|clk_cpu FD1P3AX Q reg2[5] 1.396 995.849
write_reg_u1.reg2_6_.Q top|clk_cpu FD1P3AX Q reg2[6] 1.396 995.849
write_reg_u1.reg2_7_.Q top|clk_cpu FD1P3AX Q reg2[7] 1.396 995.849
write_reg_u1.reg3_0_.Q top|clk_cpu FD1P3AX Q reg3[0] 1.396 995.849
write_reg_u1.reg3_1_.Q top|clk_cpu FD1P3AX Q reg3[1] 1.396 995.849
==============================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
- Setup time: 0.324
= Required time: 999.676
- Propagation time: 3.827
= Slack (non-critical) : 995.849
Number of logic level(s): 2
Starting point: write_reg_u1.reg2_0_.Q / Q
Ending point: read_reg_u1.data_out_0_.Q / D
The start point is clocked by top|clk_cpu [rising] on pin CK
The end point is clocked by top|clk_cpu [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------
write_reg_u1.reg2_0_.Q FD1P3AX Q Out 1.396 1.396 -
reg2[0] Net - - - - 1
read_reg_u1.data_out_8_0[0] ORCALUT4 B In 0.000 1.396 -
read_reg_u1.data_out_8_0[0] ORCALUT4 Z Out 1.216 2.611 -
read_reg_u1.data_out_8_0[0] Net - - - - 1
read_reg_u1.data_out_8[0] ORCALUT4 B In 0.000 2.611 -
read_reg_u1.data_out_8[0] ORCALUT4 Z Out 1.216 3.827 -
read_reg_u1.data_out_8[0] Net - - - - 1
read_reg_u1.data_out_0_.Q FD1P3AX D In 0.000 3.827 -
==============================================================================================
##### END OF TIMING REPORT #####]
Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]
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