top.srr

《设计与验证VerilogHDL》源码实例 和 Verilog规范

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Thu Mar 09 02:00:34 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\eda\synplicity\fpga_81\lib\lucent\ec.v"
@I::"C:\prj\Example-4-21\oe_edge\read_reg.v"
@I::"C:\prj\Example-4-21\oe_edge\decode.v"
@I::"C:\prj\Example-4-21\oe_edge\write_reg.v"
@I::"C:\prj\Example-4-21\oe_edge\top.v"
Verilog syntax check successful!
File C:\prj\Example-4-21\oe_edge\decode.v changed - recompiling
Selecting top level module top
@N:"C:\prj\Example-4-21\oe_edge\decode.v":3:7:3:12|Synthesizing module decode

@W: CL118 :"C:\prj\Example-4-21\oe_edge\decode.v":17:2:17:3|Latch generated from always block for signal CS_reg3, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:\prj\Example-4-21\oe_edge\decode.v":17:2:17:3|Latch generated from always block for signal CS_reg2, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:\prj\Example-4-21\oe_edge\decode.v":17:2:17:3|Latch generated from always block for signal CS_reg1, probably caused by a missing assignment in an if or case stmt
@N:"C:\prj\Example-4-21\oe_edge\write_reg.v":2:7:2:15|Synthesizing module write_reg

@N: CG179 :"C:\prj\Example-4-21\oe_edge\write_reg.v":29:29:29:32|Removing redundant assignment
@N: CG179 :"C:\prj\Example-4-21\oe_edge\write_reg.v":30:29:30:32|Removing redundant assignment
@N: CG179 :"C:\prj\Example-4-21\oe_edge\write_reg.v":31:29:31:32|Removing redundant assignment
@N:"C:\prj\Example-4-21\oe_edge\read_reg.v":2:7:2:14|Synthesizing module read_reg

@N:"C:\prj\Example-4-21\oe_edge\top.v":1:7:1:9|Synthesizing module top

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Mar 09 02:00:34 2006

###########################################################[
Version 8.1
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 100
Starting Generic Flow
Automatic dissolve at startup in view:work.top(verilog) of read_reg_u1(read_reg)
Automatic dissolve at startup in view:work.top(verilog) of decode_u1(decode)

Warning: Forcing use of GSR for flip-flops and
latches that do not specify sets or resets
   work.top(verilog)-decode_u1.CS_reg1.Q
   work.top(verilog)-decode_u1.CS_reg2.Q
   work.top(verilog)-decode_u1.CS_reg3.Q

@N: MT204 |Autoconstrain Mode is ON
@W: BN132 :"c:\prj\example-4-21\oe_edge\top.v":16:7:16:15|Removing instance decode_u1.my_wr_0_a2,  because it is equivalent to instance g0_0_a2_0_a2_0
---------------------------------------
Resource Usage Report
Part: lfec1e-3

Register bits: 32 of 1536 (2%)
Latch bits:      3
I/O cells:       20

Details:
BB:             8
FD1P3AX:        32
FD1S1A:         3
GSR:            1
IB:             12
INV:            1
ORCALUT4:       34
VHI:            1
VLO:            1
Found clock top|CS_ with period 1132.27ns 
Found clock top|OE_ with period 3.53ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Mar 09 02:00:37 2006
#


Top view:               top
Requested Frequency:    0.9 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -4.869

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
top|CS_            0.9 MHz       0.9 MHz       1132.268      1137.137      -4.869     inferred     Autoconstr_clkgroup_0
top|OE_            283.4 MHz     0.5 MHz       3.528         2098.494      -0.623     inferred     Autoconstr_clkgroup_0
========================================================================================================================


@W: MT118 |Paths from clock (top|CS_:f) to clock (top|OE_:r) are overconstrained because the required time of 0.01 ns is too small.  



Clock Relationships
*******************

Clocks             |    rise  to  rise    |    fall  to  fall      |    rise  to  fall   |    fall  to  rise  
--------------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack   |  constraint  slack     |  constraint  slack  |  constraint  slack 
--------------------------------------------------------------------------------------------------------------
top|CS_   top|CS_  |  No paths    -       |  1132.268    1128.588  |  No paths    -      |  No paths    -     
top|CS_   top|OE_  |  No paths    -       |  No paths    -         |  No paths    -      |  0.008       -4.869
top|OE_   top|OE_  |  3.528       -0.623  |  No paths    -         |  No paths    -      |  No paths    -     
==============================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: top|CS_
====================================



Starting Points with Worst Slack
********************************

                        Starting                                     Arrival           
Instance                Reference     Type       Pin     Net         Time        Slack 
                        Clock                                                          
---------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q     top|CS_       FD1S1A     Q       CS_reg2     2.122       -4.869
decode_u1.CS_reg1.Q     top|CS_       FD1S1A     Q       CS_reg1     2.140       -3.672
decode_u1.CS_reg3.Q     top|CS_       FD1S1A     Q       CS_reg3     1.653       -2.334
=======================================================================================


Ending Points with Worst Slack
******************************

                        Starting                                                 Required             
Instance                Reference     Type       Pin     Net                     Time         Slack   
                        Clock                                                                         
------------------------------------------------------------------------------------------------------
decode_u1.CS_reg1.Q     top|CS_       FD1S1A     D       decode_u1.CS_reg1_1     1131.944     1128.588
decode_u1.CS_reg2.Q     top|CS_       FD1S1A     D       decode_u1.CS_reg2_1     1131.944     1128.607
decode_u1.CS_reg3.Q     top|CS_       FD1S1A     D       decode_u1.CS_reg3_1     1131.944     1129.076
======================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        0.008
    - Setup time:                            0.324
    = Required time:                         -0.316

    - Propagation time:                      4.553
    = Slack (critical) :                     -4.869

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg2.Q / Q
    Ending point:                            read_reg_u1.data_out_0_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q             FD1S1A       Q        Out     2.122     2.122       -         
CS_reg2                         Net          -        -       -         -           12        
read_reg_u1.data_out_8_0[0]     ORCALUT4     A        In      0.000     2.122       -         
read_reg_u1.data_out_8_0[0]     ORCALUT4     Z        Out     1.216     3.337       -         
read_reg_u1.data_out_8_0[0]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[0]       ORCALUT4     B        In      0.000     3.337       -         
read_reg_u1.data_out_8[0]       ORCALUT4     Z        Out     1.216     4.553       -         
read_reg_u1.data_out_8[0]       Net          -        -       -         -           1         
read_reg_u1.data_out_0_.Q       FD1P3AX      D        In      0.000     4.553       -         
==============================================================================================


Path information for path number 2: 
    Requested Period:                        0.008
    - Setup time:                            0.324
    = Required time:                         -0.316

    - Propagation time:                      4.553
    = Slack (critical) :                     -4.869

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg2.Q / Q
    Ending point:                            read_reg_u1.data_out_1_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q             FD1S1A       Q        Out     2.122     2.122       -         
CS_reg2                         Net          -        -       -         -           12        
read_reg_u1.data_out_8_0[1]     ORCALUT4     A        In      0.000     2.122       -         
read_reg_u1.data_out_8_0[1]     ORCALUT4     Z        Out     1.216     3.337       -         
read_reg_u1.data_out_8_0[1]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[1]       ORCALUT4     B        In      0.000     3.337       -         
read_reg_u1.data_out_8[1]       ORCALUT4     Z        Out     1.216     4.553       -         
read_reg_u1.data_out_8[1]       Net          -        -       -         -           1         
read_reg_u1.data_out_1_.Q       FD1P3AX      D        In      0.000     4.553       -         
==============================================================================================


Path information for path number 3: 
    Requested Period:                        0.008
    - Setup time:                            0.324
    = Required time:                         -0.316

    - Propagation time:                      4.553
    = Slack (critical) :                     -4.869

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg2.Q / Q
    Ending point:                            read_reg_u1.data_out_2_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q             FD1S1A       Q        Out     2.122     2.122       -         
CS_reg2                         Net          -        -       -         -           12        
read_reg_u1.data_out_8_0[2]     ORCALUT4     A        In      0.000     2.122       -         
read_reg_u1.data_out_8_0[2]     ORCALUT4     Z        Out     1.216     3.337       -         
read_reg_u1.data_out_8_0[2]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[2]       ORCALUT4     B        In      0.000     3.337       -