decode.prf

《设计与验证VerilogHDL》源码实例 和 Verilog规范

#
# Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R.
#

# Period Constraints
FREQUENCY PORT "CS_" 277.1 MHz;
# Output Constraints
# Input Constraints

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.