decode.srr

《设计与验证VerilogHDL》源码实例 和 Verilog规范

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Thu Mar 09 02:05:13 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\eda\synplicity\fpga_81\lib\lucent\ec.v"
@I::"C:\prj\Example-4-21\asyn_bad\write_reg.v"
@I::"C:\prj\Example-4-21\asyn_bad\top.v"
@I::"C:\prj\Example-4-21\asyn_bad\read_reg.v"
@I::"C:\prj\Example-4-21\asyn_bad\decode.v"
Verilog syntax check successful!
Selecting top level module top
@N:"C:\prj\Example-4-21\asyn_bad\decode.v":3:7:3:12|Synthesizing module decode

@W: CL118 :"C:\prj\Example-4-21\asyn_bad\decode.v":17:2:17:3|Latch generated from always block for signal CS_reg3, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:\prj\Example-4-21\asyn_bad\decode.v":17:2:17:3|Latch generated from always block for signal CS_reg2, probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:\prj\Example-4-21\asyn_bad\decode.v":17:2:17:3|Latch generated from always block for signal CS_reg1, probably caused by a missing assignment in an if or case stmt
@N:"C:\prj\Example-4-21\asyn_bad\write_reg.v":2:7:2:15|Synthesizing module write_reg

@N: CG179 :"C:\prj\Example-4-21\asyn_bad\write_reg.v":22:29:22:32|Removing redundant assignment
@N: CG179 :"C:\prj\Example-4-21\asyn_bad\write_reg.v":23:29:23:32|Removing redundant assignment
@N: CG179 :"C:\prj\Example-4-21\asyn_bad\write_reg.v":24:29:24:32|Removing redundant assignment
@W: CL118 :"C:\prj\Example-4-21\asyn_bad\write_reg.v":11:12:11:13|Latch generated from always block for signal reg3[7:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:\prj\Example-4-21\asyn_bad\write_reg.v":11:12:11:13|Latch generated from always block for signal reg2[7:0], probably caused by a missing assignment in an if or case stmt
@W: CL118 :"C:\prj\Example-4-21\asyn_bad\write_reg.v":11:12:11:13|Latch generated from always block for signal reg1[7:0], probably caused by a missing assignment in an if or case stmt
@W: CL159 :"C:\prj\Example-4-21\asyn_bad\write_reg.v":4:13:4:15|Input rst is unused
@N:"C:\prj\Example-4-21\asyn_bad\read_reg.v":2:7:2:14|Synthesizing module read_reg

@W: CL118 :"C:\prj\Example-4-21\asyn_bad\read_reg.v":11:12:11:13|Latch generated from always block for signal data_out[7:0], probably caused by a missing assignment in an if or case stmt
@W: CL159 :"C:\prj\Example-4-21\asyn_bad\read_reg.v":4:13:4:15|Input rst is unused
@N:"C:\prj\Example-4-21\asyn_bad\top.v":1:7:1:9|Synthesizing module top

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Mar 09 02:05:13 2006

###########################################################[
Version 8.1
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 100
Starting Generic Flow
Automatic dissolve at startup in view:work.top(verilog) of read_reg_u1(read_reg)
Automatic dissolve at startup in view:work.top(verilog) of write_reg_u1(write_reg)
Automatic dissolve at startup in view:work.top(verilog) of decode_u1(decode)

Warning: Forcing use of GSR for flip-flops and
latches that do not specify sets or resets
   work.top(verilog)-decode_u1.CS_reg1.Q
   work.top(verilog)-decode_u1.CS_reg2.Q
   work.top(verilog)-decode_u1.CS_reg3.Q
   work.top(verilog)-write_reg_u1.reg1_0_.Q
   work.top(verilog)-write_reg_u1.reg1_1_.Q
   work.top(verilog)-write_reg_u1.reg1_2_.Q
   work.top(verilog)-write_reg_u1.reg1_3_.Q
   work.top(verilog)-write_reg_u1.reg1_4_.Q
   work.top(verilog)-write_reg_u1.reg1_5_.Q
   work.top(verilog)-write_reg_u1.reg1_6_.Q
   work.top(verilog)-write_reg_u1.reg1_7_.Q
   work.top(verilog)-write_reg_u1.reg2_0_.Q
   work.top(verilog)-write_reg_u1.reg2_1_.Q
   work.top(verilog)-write_reg_u1.reg2_2_.Q
   work.top(verilog)-write_reg_u1.reg2_3_.Q
   work.top(verilog)-write_reg_u1.reg2_4_.Q
   work.top(verilog)-write_reg_u1.reg2_5_.Q
   work.top(verilog)-write_reg_u1.reg2_6_.Q
   work.top(verilog)-write_reg_u1.reg2_7_.Q
   work.top(verilog)-write_reg_u1.reg3_0_.Q
   work.top(verilog)-write_reg_u1.reg3_1_.Q
   work.top(verilog)-write_reg_u1.reg3_2_.Q
   work.top(verilog)-write_reg_u1.reg3_3_.Q
   work.top(verilog)-write_reg_u1.reg3_4_.Q
   work.top(verilog)-write_reg_u1.reg3_5_.Q
   work.top(verilog)-write_reg_u1.reg3_6_.Q
   work.top(verilog)-write_reg_u1.reg3_7_.Q

@N: MT204 |Autoconstrain Mode is ON
---------------------------------------
Resource Usage Report
Part: lfec1e-3

Register bits: 0 of 1536 (0%)
Latch bits:      35
I/O cells:       19

Details:
BB:             8
FD1S1A:         35
GSR:            1
IB:             11
INV:            2
ORCALUT4:       34
PFUMX:          8
VHI:            1
VLO:            1
Found clock top|CS_ with period 3.61ns 
@W:"c:\prj\example-4-21\asyn_bad\top.v":39:9:39:19|Net read_reg_u1.N_14_i appears to be a clock source which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Mar 09 02:05:15 2006
#


Top view:               top
Requested Frequency:    277.1 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -0.637

                   Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group                
------------------------------------------------------------------------------------------------------------------------
top|CS_            277.1 MHz     235.6 MHz     3.608         4.245         -0.637     inferred     Autoconstr_clkgroup_0
========================================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise   |    fall  to  fall    |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack  |  constraint  slack   |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------
top|CS_   top|CS_  |  No paths    -      |  3.608       -0.637  |  No paths    -      |  No paths    -    
==========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: top|CS_
====================================



Starting Points with Worst Slack
********************************

                           Starting                                     Arrival           
Instance                   Reference     Type       Pin     Net         Time        Slack 
                           Clock                                                          
------------------------------------------------------------------------------------------
decode_u1.CS_reg1.Q        top|CS_       FD1S1A     Q       CS_reg1     2.159       -0.637
decode_u1.CS_reg2.Q        top|CS_       FD1S1A     Q       CS_reg2     2.122       -0.599
write_reg_u1.reg1_0_.Q     top|CS_       FD1S1A     Q       reg1[0]     1.559       -0.036
write_reg_u1.reg1_1_.Q     top|CS_       FD1S1A     Q       reg1[1]     1.396       0.127 
write_reg_u1.reg1_2_.Q     top|CS_       FD1S1A     Q       reg1[2]     1.396       0.127 
write_reg_u1.reg1_3_.Q     top|CS_       FD1S1A     Q       reg1[3]     1.396       0.127 
write_reg_u1.reg1_4_.Q     top|CS_       FD1S1A     Q       reg1[4]     1.396       0.127 
write_reg_u1.reg1_5_.Q     top|CS_       FD1S1A     Q       reg1[5]     1.396       0.127 
write_reg_u1.reg1_6_.Q     top|CS_       FD1S1A     Q       reg1[6]     1.396       0.127 
write_reg_u1.reg1_7_.Q     top|CS_       FD1S1A     Q       reg1[7]     1.396       0.127 
==========================================================================================