mod_copy1.msg

来自「《设计与验证VerilogHDL》源码实例 和 Verilog规范」· MSG 代码 · 共 8 行

@TM:1141811788
@N:  :"":0:0:0:-1|Only System clock will be Autoconstrained
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: MT204 :"":0:0:0:-1|Autoconstrain Mode is ON
@TM:1141811854
@N:  :"c:\prj\chapter5\example-5-7\source\mod_copy2.v":1:7:1:15|Synthesizing module mod_copy1