count60.vhd

来自「基于FPGS的数字秒表设计文件 含有计时」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count60 is
port(jn,rd,clk:in std_logic;
count1,count0:out std_logic_vector(3 downto 0);
co:out std_logic);
end count60;
architecture count_arc of count60 is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if jn='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";
if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
if rd='1' then
cnt0:="0000" ; cnt1:="0000";
END IF;
count1<=cnt1;
count0<=cnt0;
end process;
end count_arc;