clkgen.vhd

来自「基于FPGS的数字秒表设计文件 含有计时」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
entity clkgen is
port(clk: in std_logic;
        newclk: out std_logic);
end clkgen;
architecture art of clkgen is
signal cnter:integer range 0 to 10#39#;
begin
process(clk)
begin
if clk'event and clk='1' then
if cnter=10#39# then cnter<=0;
else cnter<=cnter+1;
end if;
end if;
end process;
process(cnter)
begin
if cnter=10#39# then newclk<='1';
else newclk<='0';
end if;
end process;
end art;