count100.vhd

来自「基于FPGS的数字秒表设计文件 含有计时」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count100 is
port(kn,rd,clk:in std_logic;
count01,count00:out std_logic_vector(3 downto 0);
co1:out std_logic);
end count100;
architecture count_arc of count100 is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if kn='1' then
if cnt1="1001" and cnt0="1000" then
co1<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";
if cnt1<"1001" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co1<='0';
end if;
end if;
end if;
end if;
if rd='1' then

cnt0:="0000" ;cnt1:="0000";
end if;
count01<=cnt1;
count00<=cnt0;
end process;
end count_arc;