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📄 miaobiao.rpt

📁 基于FPGS的数字秒表设计文件 含有计时
💻 RPT
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** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                         Logic cells placed in LAB 'E'
        +------------------------------- LC73 |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3
        | +----------------------------- LC74 |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4
        | | +--------------------------- LC75 |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5
        | | | +------------------------- LC77 |CLKGEN:1|cnter5
        | | | | +----------------------- LC65 |CLKGEN:1|cnter4
        | | | | | +--------------------- LC66 |CLKGEN:1|cnter3
        | | | | | | +------------------- LC68 |CLKGEN:1|cnter2
        | | | | | | | +----------------- LC69 |CLKGEN:1|cnter1
        | | | | | | | | +--------------- LC71 |CLKGEN:1|cnter0
        | | | | | | | | | +------------- LC67 |COUNT60:3|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|gcp2
        | | | | | | | | | | +----------- LC76 |COUNT60:3|cnt02
        | | | | | | | | | | | +--------- LC79 |COUNT60:3|cnt01
        | | | | | | | | | | | | +------- LC70 |COUNT60:3|cnt00
        | | | | | | | | | | | | | +----- LC78 |COUNT100:2|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|gcp2
        | | | | | | | | | | | | | | +--- LC72 |COUNT100:2|cnt03
        | | | | | | | | | | | | | | | +- LC80 led41
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':
LC73 -> - - - - - * - - - - - - - - - - | - - - - * - - - | <-- |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3
LC74 -> - - - - * - - - - - - - - - - - | - - - - * - - - | <-- |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4
LC75 -> - - - * - - - - - - - - - - - - | - - - - * - - - | <-- |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5
LC77 -> - - * * * * - - - - - - - - * - | - - - - * * - - | <-- |CLKGEN:1|cnter5
LC65 -> - * * * * * - - - - - - - - * - | - - - - * * - - | <-- |CLKGEN:1|cnter4
LC66 -> * * * * * * - - - - - - - - * - | - - - - * * - - | <-- |CLKGEN:1|cnter3
LC68 -> * * * * * * * - - - - - - - * - | - - - - * * - - | <-- |CLKGEN:1|cnter2
LC69 -> * * * * * * * * - - - - - - * - | - - - - * * - - | <-- |CLKGEN:1|cnter1
LC71 -> * * * * * * * * * - - - - - * - | - - - - * * - - | <-- |CLKGEN:1|cnter0
LC76 -> - - - - - - - - - * * - * - - - | - - - - * - * * | <-- |COUNT60:3|cnt02
LC79 -> - - - - - - - - - * * * * - - - | - - - - * - * * | <-- |COUNT60:3|cnt01
LC70 -> - - - - - - - - - * * * * - - - | - - - - * - * * | <-- |COUNT60:3|cnt00
LC78 -> - - - - - - - - - - - - - - * - | - - - - * - - - | <-- |COUNT100:2|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|gcp2
LC72 -> - - - - - - - - - - - - - - * * | - - - - * * - - | <-- |COUNT100:2|cnt03

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
6    -> - - - - - - - - - - * * * - * - | - * - - * * - * | <-- reset
5    -> - - - - - - - - - - * * * - * - | - * - - * * - * | <-- setmin
LC122-> - - - - - - - - - - * * * - - - | - - - - * - * * | <-- |COUNT60:3|cnt03
LC82 -> - - - - - - - - - - * * * - - - | - - - - * * - * | <-- |COUNT100:2|:12
LC81 -> - - - - - - - - - - - - - * * * | - - - - * * - - | <-- |COUNT100:2|cnt02
LC92 -> - - - - - - - - - - - - - * * * | - - - - * * - - | <-- |COUNT100:2|cnt01
LC95 -> - - - - - - - - - - - - - * * * | - - - - * * - - | <-- |COUNT100:2|cnt00


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             f:\keshe\miaobiao.rpt
miaobiao

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                         Logic cells placed in LAB 'F'
        +------------------------------- LC87 |COUNT100:2|LPM_ADD_SUB:118|addcore:adder|addcore:adder0|gcp2
        | +----------------------------- LC82 |COUNT100:2|:12
        | | +--------------------------- LC81 |COUNT100:2|cnt02
        | | | +------------------------- LC92 |COUNT100:2|cnt01
        | | | | +----------------------- LC95 |COUNT100:2|cnt00
        | | | | | +--------------------- LC96 |COUNT100:2|cnt13
        | | | | | | +------------------- LC90 |COUNT100:2|cnt12
        | | | | | | | +----------------- LC84 |COUNT100:2|cnt11
        | | | | | | | | +--------------- LC89 |COUNT100:2|cnt10
        | | | | | | | | | +------------- LC94 led34
        | | | | | | | | | | +----------- LC93 led35
        | | | | | | | | | | | +--------- LC91 led36
        | | | | | | | | | | | | +------- LC88 led37
        | | | | | | | | | | | | | +----- LC86 led38
        | | | | | | | | | | | | | | +--- LC85 led39
        | | | | | | | | | | | | | | | +- LC83 led40
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC87 -> - - - - - * - - - - - - - - - - | - - - - - * - - | <-- |COUNT100:2|LPM_ADD_SUB:118|addcore:adder|addcore:adder0|gcp2
LC82 -> - * - - - - - - - - - - - - - - | - - - - * * - * | <-- |COUNT100:2|:12
LC81 -> - * * - * * * * * - * * * * * * | - - - - * * - - | <-- |COUNT100:2|cnt02
LC92 -> - * * * * * * * * - * * * * * * | - - - - * * - - | <-- |COUNT100:2|cnt01
LC95 -> - * * * * * * * * - * * * * * * | - - - - * * - - | <-- |COUNT100:2|cnt00
LC96 -> - * - - - * * * * * - - - - - - | - - - - - * * - | <-- |COUNT100:2|cnt13
LC90 -> * * - - - * * - * * - - - - - - | - - - - - * * - | <-- |COUNT100:2|cnt12
LC84 -> * * - - - * * * * * - - - - - - | - - - - - * * - | <-- |COUNT100:2|cnt11
LC89 -> * * - - - * * * * * - - - - - - | - - - - - * * - | <-- |COUNT100:2|cnt10

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
6    -> - - * * * * * * * - - - - - - - | - * - - * * - * | <-- reset
5    -> - * * * * * * * * - - - - - - - | - * - - * * - * | <-- setmin
LC77 -> - * * * * * * * * - - - - - - - | - - - - * * - - | <-- |CLKGEN:1|cnter5
LC65 -> - * * * * * * * * - - - - - - - | - - - - * * - - | <-- |CLKGEN:1|cnter4
LC66 -> - * * * * * * * * - - - - - - - | - - - - * * - - | <-- |CLKGEN:1|cnter3
LC68 -> - * * * * * * * * - - - - - - - | - - - - * * - - | <-- |CLKGEN:1|cnter2
LC69 -> - * * * * * * * * - - - - - - - | - - - - * * - - | <-- |CLKGEN:1|cnter1
LC71 -> - * * * * * * * * - - - - - - - | - - - - * * - - | <-- |CLKGEN:1|cnter0
LC72 -> - * * * * * * * * - * * * * * * | - - - - * * - - | <-- |COUNT100:2|cnt03


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             f:\keshe\miaobiao.rpt
miaobiao

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                       Logic cells placed in LAB 'G'
        +------------- LC109 led27
        | +----------- LC107 led28
        | | +--------- LC105 led29
        | | | +------- LC104 led30
        | | | | +----- LC101 led31
        | | | | | +--- LC99 led32
        | | | | | | +- LC97 led33
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':

Pin
83   -> - - - - - - - | - - - - - - - - | <-- clk
LC122-> * - - - - - - | - - - - * - * * | <-- |COUNT60:3|cnt03
LC76 -> * - - - - - - | - - - - * - * * | <-- |COUNT60:3|cnt02
LC79 -> * - - - - - - | - - - - * - * * | <-- |COUNT60:3|cnt01
LC70 -> * - - - - - - | - - - - * - * * | <-- |COUNT60:3|cnt00
LC96 -> - * * * * * * | - - - - - * * - | <-- |COUNT100:2|cnt13
LC90 -> - * * * * * * | - - - - - * * - | <-- |COUNT100:2|cnt12
LC84 -> - * * * * * * | - - - - - * * - | <-- |COUNT100:2|cnt11
LC89 -> - * * * * * * | - - - - - * * - | <-- |COUNT100:2|cnt10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             f:\keshe\miaobiao.rpt
miaobiao

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                     Logic cells placed in LAB 'H'
        +--------------------------- LC116 |COUNT60:3|:12
        | +------------------------- LC122 |COUNT60:3|cnt03
        | | +----------------------- LC124 |COUNT60:3|cnt13
        | | | +--------------------- LC113 |COUNT60:3|cnt12
        | | | | +------------------- LC114 |COUNT60:3|cnt11
        | | | | | +----------------- LC121 |COUNT60:3|cnt10
        | | | | | | +--------------- LC128 led19
        | | | | | | | +------------- LC126 led20
        | | | | | | | | +----------- LC125 led21
        | | | | | | | | | +--------- LC123 led22
        | | | | | | | | | | +------- LC120 led23
        | | | | | | | | | | | +----- LC118 led24
        | | | | | | | | | | | | +--- LC117 led25
        | | | | | | | | | | | | | +- LC115 led26
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC116-> * - - - - - - - - - - - - - | - * - - - - - * | <-- |COUNT60:3|:12
LC122-> * * * * * * - - * * * * * * | - - - - * - * * | <-- |COUNT60:3|cnt03
LC124-> * - * * * * * * - - - - - - | - - * - - - - * | <-- |COUNT60:3|cnt13
LC113-> * - - * * * * * - - - - - - | - - * - - - - * | <-- |COUNT60:3|cnt12
LC114-> * - - * * * * * - - - - - - | - - * - - - - * | <-- |COUNT60:3|cnt11
LC121-> * - - * * * * * - - - - - - | - - * - - - - * | <-- |COUNT60:3|cnt10

Pin
83   -> - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
6    -> - * * * * * - - - - - - - - | - * - - * * - * | <-- reset
5    -> * * * * * * - - - - - - - - | - * - - * * - * | <-- setmin
LC67 -> - * - - - - - - - - - - - - | - - - - - - - * | <-- |COUNT60:3|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|gcp2
LC76 -> * * * * * * - - * * * * * * | - - - - * - * * | <-- |COUNT60:3|cnt02
LC79 -> * * * * * * - - * * * * * * | - - - - * - * * | <-- |COUNT60:3|cnt01
LC70 -> * * * * * * - - * * * * * * | - - - - * - * * | <-- |COUNT60:3|cnt00
LC82 -> * * * * * * - - - - - - - - | - - - - * * - * | <-- |COUNT100:2|:12


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                             f:\keshe\miaobiao.rpt
miaobiao

** EQUATIONS **

clk      : INPUT;
reset    : INPUT;
setmin   : INPUT;

-- Node name is 'led0' 
-- Equation name is 'led0', location is LC011, type is output.
 led0    = LCELL( _EQ001 $  VCC);
  _EQ001 = !_LC018 &  _LC022 &  _LC031 &  _LC032
         #  _LC018 &  _LC022 &  _LC031 & !_LC032
         # !_LC018 &  _LC022 & !_LC031 & !_LC032
         # !_LC018 & !_LC022 & !_LC031 &  _LC032;

-- Node name is 'led1' 
-- Equation name is 'led1', location is LC008, type is output.
 led1    = LCELL( _EQ002 $  VCC);
  _EQ002 = !_LC018 &  _LC022 & !_LC031 &  _LC032
         #  _LC018 &  _LC022 &  _LC031
         #  _LC018 & !_LC022 &  _LC032
         # !_LC022 &  _LC031 &  _LC032;

-- Node name is 'led2' 
-- Equation name is 'led2', location is LC006, type is output.
 led2    = LCELL( _EQ003 $  VCC);
  _EQ003 =  _LC018 & !_LC022 & !_LC031 & !_LC032
         #  _LC018 &  _LC031 &  _LC032
         # !_LC022 &  _LC031 &  _LC032;

-- Node name is 'led3' 
-- Equation name is 'led3', location is LC005, type is output.
 led3    = LCELL( _EQ004 $  VCC);
  _EQ004 =  _LC018 & !_LC022 &  _LC031 & !_LC032
         # !_LC018 &  _LC022 & !_LC031 & !_LC032
         # !_LC018 & !_LC022 & !_LC031 &  _LC032
         #  _LC018 &  _LC022 &  _LC032;

-- Node name is 'led4' 
-- Equation name is 'led4', location is LC003, type is output.
 led4    = LCELL( _EQ005 $  VCC);
  _EQ005 = !_LC018 & !_LC031 &  _LC032
         # !_LC018 &  _LC022 & !_LC032
         #  _LC022 & !_LC031;

-- Node name is 'led5' 
-- Equation name is 'led5', location is LC029, type is output.
 led5    = LCELL( _EQ006 $  VCC);
  _EQ006 = !_LC018 &  _LC022 &  _LC031 &  _LC032
         # !_LC018 &  _LC022 & !_LC031 & !_LC032
         #  _LC018 & !_LC022 & !_LC031 & !_LC032
         #  _LC018 &  _LC022 & !_LC031;

-- Node name is 'led6' 
-- Equation name is 'led6', location is LC027, type is output.
 led6    = LCELL( _EQ007 $  VCC);
  _EQ007 =  _LC018 &  _LC022 & !_LC031 &  _LC032
         # !_LC018 & !_LC022 &  _LC031 &  _LC032
         # !_LC018 & !_LC031 & !_LC032;

-- Node name is 'led7' 
-- Equation name is 'led7', location is LC025, type is output.
 led7    = LCELL( _EQ008 $  VCC);
  _EQ008 = !_LC023 &  _LC026 &  _LC028 &  _LC030
         #  _LC023 &  _LC026 & !_LC028 &  _LC030
         # !_LC023 &  _LC026 & !_LC028 & !_LC030
         # !_LC023 & !_LC026 &  _LC028 & !_LC030;

-- Node name is 'led8' 
-- Equation name is 'led8', location is LC024, type is output.
 led8    = LCELL( _EQ009 $  VCC);
  _EQ009 = !_LC023 &  _LC026 &  _LC028 & !_LC030
         #  _LC023 &  _LC026 &  _LC030
         #  _LC023 & !_LC026 &  _LC028
         # !_LC026 &  _LC028 &  _LC030;

-- Node name is 'led9' 
-- Equation name is 'led9', location is LC021, type is output.
 led9    = LCELL( _EQ010 $  VCC);
  _EQ010 =  _LC023 & !_LC026 & !_LC028 & !_LC030

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