miaobiao.rpt
来自「基于FPGS的数字秒表设计文件 含有计时」· RPT 代码 · 共 1,379 行 · 第 1/5 页
RPT
1,379 行
Total flipflops required: 32
Total product terms required: 301
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 23
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: f:\keshe\miaobiao.rpt
miaobiao
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 clk
6 (13) (A) INPUT 0 0 0 0 0 0 24 reset
5 (14) (A) INPUT 0 0 0 0 0 0 26 setmin
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\keshe\miaobiao.rpt
miaobiao
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
8 11 A OUTPUT t 0 0 0 0 4 0 0 led0
9 8 A OUTPUT t 0 0 0 0 4 0 0 led1
10 6 A OUTPUT t 0 0 0 0 4 0 0 led2
11 5 A OUTPUT t 0 0 0 0 4 0 0 led3
12 3 A OUTPUT t 0 0 0 0 4 0 0 led4
15 29 B OUTPUT t 0 0 0 0 4 0 0 led5
16 27 B OUTPUT t 0 0 0 0 4 0 0 led6
17 25 B OUTPUT t 0 0 0 0 4 0 0 led7
18 24 B OUTPUT t 0 0 0 0 4 0 0 led8
20 21 B OUTPUT t 0 0 0 0 4 0 0 led9
21 19 B OUTPUT t 0 0 0 0 4 0 0 led10
22 17 B OUTPUT t 0 0 0 0 4 0 0 led11
24 46 C OUTPUT t 0 0 0 0 4 0 0 led12
25 45 C OUTPUT t 0 0 0 0 4 0 0 led13
27 43 C OUTPUT t 0 0 0 0 4 0 0 led14
28 40 C OUTPUT t 0 0 0 0 4 0 0 led15
29 38 C OUTPUT t 0 0 0 0 4 0 0 led16
30 37 C OUTPUT t 0 0 0 0 4 0 0 led17
31 35 C OUTPUT t 0 0 0 0 4 0 0 led18
81 128 H OUTPUT t 0 0 0 0 4 0 0 led19
80 126 H OUTPUT t 0 0 0 0 4 0 0 led20
79 125 H OUTPUT t 0 0 0 0 4 0 0 led21
77 123 H OUTPUT t 0 0 0 0 4 0 0 led22
76 120 H OUTPUT t 0 0 0 0 4 0 0 led23
75 118 H OUTPUT t 0 0 0 0 4 0 0 led24
74 117 H OUTPUT t 0 0 0 0 4 0 0 led25
73 115 H OUTPUT t 0 0 0 0 4 0 0 led26
70 109 G OUTPUT t 0 0 0 0 4 0 0 led27
69 107 G OUTPUT t 0 0 0 0 4 0 0 led28
68 105 G OUTPUT t 0 0 0 0 4 0 0 led29
67 104 G OUTPUT t 0 0 0 0 4 0 0 led30
65 101 G OUTPUT t 0 0 0 0 4 0 0 led31
64 99 G OUTPUT t 0 0 0 0 4 0 0 led32
63 97 G OUTPUT t 0 0 0 0 4 0 0 led33
61 94 F OUTPUT t 0 0 0 0 4 0 0 led34
60 93 F OUTPUT t 0 0 0 0 4 0 0 led35
58 91 F OUTPUT t 0 0 0 0 4 0 0 led36
57 88 F OUTPUT t 0 0 0 0 4 0 0 led37
56 86 F OUTPUT t 0 0 0 0 4 0 0 led38
55 85 F OUTPUT t 0 0 0 0 4 0 0 led39
54 83 F OUTPUT t 0 0 0 0 4 0 0 led40
52 80 E OUTPUT t 0 0 0 0 4 0 0 led41
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\keshe\miaobiao.rpt
miaobiao
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(49) 73 E SOFT t 0 0 0 0 4 0 1 |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node3
- 74 E SOFT t 0 0 0 0 5 0 1 |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node4
(50) 75 E SOFT t 0 0 0 0 6 0 1 |CLKGEN:1|LPM_ADD_SUB:78|addcore:adder|addcore:adder0|result_node5
(51) 77 E DFFE + t 0 0 0 0 7 0 13 |CLKGEN:1|cnter5 (|CLKGEN:1|:3)
(44) 65 E DFFE + t 0 0 0 0 7 0 14 |CLKGEN:1|cnter4 (|CLKGEN:1|:4)
- 66 E DFFE + t 0 0 0 0 7 0 15 |CLKGEN:1|cnter3 (|CLKGEN:1|:5)
- 68 E TFFE + t 0 0 0 0 2 0 15 |CLKGEN:1|cnter2 (|CLKGEN:1|:6)
(46) 69 E TFFE + t 0 0 0 0 1 0 16 |CLKGEN:1|cnter1 (|CLKGEN:1|:7)
- 71 E TFFE + t 0 0 0 0 0 0 17 |CLKGEN:1|cnter0 (|CLKGEN:1|:8)
(45) 67 E SOFT t 0 0 0 0 3 0 1 |COUNT60:3|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|gcp2
- 116 H TFFE t 2 1 0 1 10 0 9 |COUNT60:3|:12
- 122 H TFFE t 2 0 0 2 6 7 9 |COUNT60:3|cnt03 (|COUNT60:3|:14)
- 76 E TFFE t 1 0 1 2 5 7 9 |COUNT60:3|cnt02 (|COUNT60:3|:15)
- 79 E TFFE t 1 0 1 2 4 7 10 |COUNT60:3|cnt01 (|COUNT60:3|:16)
- 70 E DFFE t 1 0 1 2 5 7 10 |COUNT60:3|cnt00 (|COUNT60:3|:17)
- 124 H TFFE t 1 1 0 2 6 7 5 |COUNT60:3|cnt13 (|COUNT60:3|:18)
- 113 H TFFE t 2 1 0 2 9 7 4 |COUNT60:3|cnt12 (|COUNT60:3|:19)
- 114 H TFFE t 2 1 0 2 9 7 4 |COUNT60:3|cnt11 (|COUNT60:3|:20)
- 121 H TFFE t 3 1 0 2 9 7 4 |COUNT60:3|cnt10 (|COUNT60:3|:21)
- 20 B SOFT t 0 0 0 0 3 0 1 |COUNT60:5|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|gcp2
- 30 B TFFE t 2 0 0 2 6 7 8 |COUNT60:5|cnt03 (|COUNT60:5|:14)
- 28 B TFFE t 1 0 1 2 5 7 8 |COUNT60:5|cnt02 (|COUNT60:5|:15)
- 23 B TFFE t 1 0 1 2 4 7 9 |COUNT60:5|cnt01 (|COUNT60:5|:16)
- 26 B DFFE t 1 0 1 2 5 7 9 |COUNT60:5|cnt00 (|COUNT60:5|:17)
- 31 B TFFE t 1 1 0 2 6 7 4 |COUNT60:5|cnt13 (|COUNT60:5|:18)
(14) 32 B TFFE t 2 1 0 2 9 7 3 |COUNT60:5|cnt12 (|COUNT60:5|:19)
- 18 B TFFE t 2 1 0 2 9 7 3 |COUNT60:5|cnt11 (|COUNT60:5|:20)
- 22 B TFFE t 3 1 0 2 9 7 3 |COUNT60:5|cnt10 (|COUNT60:5|:21)
- 78 E SOFT t 0 0 0 0 3 0 1 |COUNT100:2|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|gcp2
- 87 F SOFT t 0 0 0 0 3 0 1 |COUNT100:2|LPM_ADD_SUB:118|addcore:adder|addcore:adder0|gcp2
- 82 F TFFE t 2 0 1 1 15 0 10 |COUNT100:2|:12
(48) 72 E TFFE t 2 0 0 2 11 7 9 |COUNT100:2|cnt03 (|COUNT100:2|:14)
- 81 F TFFE t 1 0 1 2 10 7 9 |COUNT100:2|cnt02 (|COUNT100:2|:15)
- 92 F TFFE t 1 0 1 2 9 7 10 |COUNT100:2|cnt01 (|COUNT100:2|:16)
- 95 F DFFE t 1 0 1 2 10 7 10 |COUNT100:2|cnt00 (|COUNT100:2|:17)
(62) 96 F TFFE t 3 1 0 2 15 7 5 |COUNT100:2|cnt13 (|COUNT100:2|:18)
- 90 F TFFE t 2 1 1 2 14 7 5 |COUNT100:2|cnt12 (|COUNT100:2|:19)
- 84 F TFFE t 2 1 1 2 13 7 6 |COUNT100:2|cnt11 (|COUNT100:2|:20)
- 89 F TFFE t 3 0 1 2 14 7 6 |COUNT100:2|cnt10 (|COUNT100:2|:21)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\keshe\miaobiao.rpt
miaobiao
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------- LC11 led0
| +------- LC8 led1
| | +----- LC6 led2
| | | +--- LC5 led3
| | | | +- LC3 led4
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'A'
LC | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
83 -> - - - - - | - - - - - - - - | <-- clk
LC31 -> * * * * * | * * - - - - - - | <-- |COUNT60:5|cnt13
LC32 -> * * * * * | * * - - - - - - | <-- |COUNT60:5|cnt12
LC18 -> * * * * * | * * - - - - - - | <-- |COUNT60:5|cnt11
LC22 -> * * * * * | * * - - - - - - | <-- |COUNT60:5|cnt10
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\keshe\miaobiao.rpt
miaobiao
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC20 |COUNT60:5|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|gcp2
| +----------------------------- LC30 |COUNT60:5|cnt03
| | +--------------------------- LC28 |COUNT60:5|cnt02
| | | +------------------------- LC23 |COUNT60:5|cnt01
| | | | +----------------------- LC26 |COUNT60:5|cnt00
| | | | | +--------------------- LC31 |COUNT60:5|cnt13
| | | | | | +------------------- LC32 |COUNT60:5|cnt12
| | | | | | | +----------------- LC18 |COUNT60:5|cnt11
| | | | | | | | +--------------- LC22 |COUNT60:5|cnt10
| | | | | | | | | +------------- LC29 led5
| | | | | | | | | | +----------- LC27 led6
| | | | | | | | | | | +--------- LC25 led7
| | | | | | | | | | | | +------- LC24 led8
| | | | | | | | | | | | | +----- LC21 led9
| | | | | | | | | | | | | | +--- LC19 led10
| | | | | | | | | | | | | | | +- LC17 led11
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC20 -> - * - - - - - - - - - - - - - - | - * - - - - - - | <-- |COUNT60:5|LPM_ADD_SUB:91|addcore:adder|addcore:adder0|gcp2
LC30 -> - * * * * * * * * - - * * * * * | - * * - - - - - | <-- |COUNT60:5|cnt03
LC28 -> * * * - * * * * * - - * * * * * | - * * - - - - - | <-- |COUNT60:5|cnt02
LC23 -> * * * * * * * * * - - * * * * * | - * * - - - - - | <-- |COUNT60:5|cnt01
LC26 -> * * * * * * * * * - - * * * * * | - * * - - - - - | <-- |COUNT60:5|cnt00
LC31 -> - - - - - * * * * * * - - - - - | * * - - - - - - | <-- |COUNT60:5|cnt13
LC32 -> - - - - - - * * * * * - - - - - | * * - - - - - - | <-- |COUNT60:5|cnt12
LC18 -> - - - - - - * * * * * - - - - - | * * - - - - - - | <-- |COUNT60:5|cnt11
LC22 -> - - - - - - * * * * * - - - - - | * * - - - - - - | <-- |COUNT60:5|cnt10
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
6 -> - * * * * * * * * - - - - - - - | - * - - * * - * | <-- reset
5 -> - * * * * * * * * - - - - - - - | - * - - * * - * | <-- setmin
LC116-> - * * * * * * * * - - - - - - - | - * - - - - - * | <-- |COUNT60:3|:12
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\keshe\miaobiao.rpt
miaobiao
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------- LC46 led12
| +----------- LC45 led13
| | +--------- LC43 led14
| | | +------- LC40 led15
| | | | +----- LC38 led16
| | | | | +--- LC37 led17
| | | | | | +- LC35 led18
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'C'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
Pin
83 -> - - - - - - - | - - - - - - - - | <-- clk
LC124-> - - * * * * * | - - * - - - - * | <-- |COUNT60:3|cnt13
LC113-> - - * * * * * | - - * - - - - * | <-- |COUNT60:3|cnt12
LC114-> - - * * * * * | - - * - - - - * | <-- |COUNT60:3|cnt11
LC121-> - - * * * * * | - - * - - - - * | <-- |COUNT60:3|cnt10
LC30 -> * * - - - - - | - * * - - - - - | <-- |COUNT60:5|cnt03
LC28 -> * * - - - - - | - * * - - - - - | <-- |COUNT60:5|cnt02
LC23 -> * * - - - - - | - * * - - - - - | <-- |COUNT60:5|cnt01
LC26 -> * * - - - - - | - * * - - - - - | <-- |COUNT60:5|cnt00
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\keshe\miaobiao.rpt
miaobiao
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