📄 miaobiao.rpt
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Project Information f:\keshe\miaobiao.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 02/27/2009 08:19:02
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
miaobiao EPM7128SLC84-15 3 42 0 81 23 63 %
User Pins: 3 42 0
Project Information f:\keshe\miaobiao.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information f:\keshe\miaobiao.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
miaobiao@83 clk
miaobiao@8 led0
miaobiao@9 led1
miaobiao@10 led2
miaobiao@11 led3
miaobiao@12 led4
miaobiao@15 led5
miaobiao@16 led6
miaobiao@17 led7
miaobiao@18 led8
miaobiao@20 led9
miaobiao@21 led10
miaobiao@22 led11
miaobiao@24 led12
miaobiao@25 led13
miaobiao@27 led14
miaobiao@28 led15
miaobiao@29 led16
miaobiao@30 led17
miaobiao@31 led18
miaobiao@81 led19
miaobiao@80 led20
miaobiao@79 led21
miaobiao@77 led22
miaobiao@76 led23
miaobiao@75 led24
miaobiao@74 led25
miaobiao@73 led26
miaobiao@70 led27
miaobiao@69 led28
miaobiao@68 led29
miaobiao@67 led30
miaobiao@65 led31
miaobiao@64 led32
miaobiao@63 led33
miaobiao@61 led34
miaobiao@60 led35
miaobiao@58 led36
miaobiao@57 led37
miaobiao@56 led38
miaobiao@55 led39
miaobiao@54 led40
miaobiao@52 led41
miaobiao@6 reset
miaobiao@5 setmin
Project Information f:\keshe\miaobiao.rpt
** FILE HIERARCHY **
|clkgen:1|
|clkgen:1|lpm_add_sub:78|
|clkgen:1|lpm_add_sub:78|addcore:adder|
|clkgen:1|lpm_add_sub:78|addcore:adder|addcore:adder0|
|clkgen:1|lpm_add_sub:78|altshift:result_ext_latency_ffs|
|clkgen:1|lpm_add_sub:78|altshift:carry_ext_latency_ffs|
|clkgen:1|lpm_add_sub:78|altshift:oflow_ext_latency_ffs|
|count100:2|
|count100:2|lpm_add_sub:91|
|count100:2|lpm_add_sub:91|addcore:adder|
|count100:2|lpm_add_sub:91|addcore:adder|addcore:adder0|
|count100:2|lpm_add_sub:91|altshift:result_ext_latency_ffs|
|count100:2|lpm_add_sub:91|altshift:carry_ext_latency_ffs|
|count100:2|lpm_add_sub:91|altshift:oflow_ext_latency_ffs|
|count100:2|lpm_add_sub:118|
|count100:2|lpm_add_sub:118|addcore:adder|
|count100:2|lpm_add_sub:118|addcore:adder|addcore:adder0|
|count100:2|lpm_add_sub:118|altshift:result_ext_latency_ffs|
|count100:2|lpm_add_sub:118|altshift:carry_ext_latency_ffs|
|count100:2|lpm_add_sub:118|altshift:oflow_ext_latency_ffs|
|count60:3|
|count60:3|lpm_add_sub:91|
|count60:3|lpm_add_sub:91|addcore:adder|
|count60:3|lpm_add_sub:91|addcore:adder|addcore:adder0|
|count60:3|lpm_add_sub:91|altshift:result_ext_latency_ffs|
|count60:3|lpm_add_sub:91|altshift:carry_ext_latency_ffs|
|count60:3|lpm_add_sub:91|altshift:oflow_ext_latency_ffs|
|count60:3|lpm_add_sub:118|
|count60:3|lpm_add_sub:118|addcore:adder|
|count60:3|lpm_add_sub:118|addcore:adder|addcore:adder0|
|count60:3|lpm_add_sub:118|altshift:result_ext_latency_ffs|
|count60:3|lpm_add_sub:118|altshift:carry_ext_latency_ffs|
|count60:3|lpm_add_sub:118|altshift:oflow_ext_latency_ffs|
|count60:5|
|count60:5|lpm_add_sub:91|
|count60:5|lpm_add_sub:91|addcore:adder|
|count60:5|lpm_add_sub:91|addcore:adder|addcore:adder0|
|count60:5|lpm_add_sub:91|altshift:result_ext_latency_ffs|
|count60:5|lpm_add_sub:91|altshift:carry_ext_latency_ffs|
|count60:5|lpm_add_sub:91|altshift:oflow_ext_latency_ffs|
|count60:5|lpm_add_sub:118|
|count60:5|lpm_add_sub:118|addcore:adder|
|count60:5|lpm_add_sub:118|addcore:adder|addcore:adder0|
|count60:5|lpm_add_sub:118|altshift:result_ext_latency_ffs|
|count60:5|lpm_add_sub:118|altshift:carry_ext_latency_ffs|
|count60:5|lpm_add_sub:118|altshift:oflow_ext_latency_ffs|
|decl7s:6|
|decl7s:11|
|decl7s:10|
|decl7s:9|
|decl7s:8|
|decl7s:7|
Device-Specific Information: f:\keshe\miaobiao.rpt
miaobiao
***** Logic for device 'miaobiao' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R
E
s S V
r e E C l l l V l l l
l l l l e t R C e e e C e e e
e e e e G s m V I G G G c G d d d C d d d
d d d d N e i E N N N N l N 1 2 2 I 2 2 2
3 2 1 0 D t n D T D D D k D 9 0 1 O 2 3 4
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
led4 | 12 74 | led25
VCCIO | 13 73 | led26
#TDI | 14 72 | GND
led5 | 15 71 | #TDO
led6 | 16 70 | led27
led7 | 17 69 | led28
led8 | 18 68 | led29
GND | 19 67 | led30
led9 | 20 66 | VCCIO
led10 | 21 65 | led31
led11 | 22 EPM7128SLC84-15 64 | led32
#TMS | 23 63 | led33
led12 | 24 62 | #TCK
led13 | 25 61 | led34
VCCIO | 26 60 | led35
led14 | 27 59 | GND
led15 | 28 58 | led36
led16 | 29 57 | led37
led17 | 30 56 | led38
led18 | 31 55 | led39
GND | 32 54 | led40
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R R V R R R G V R R R G R R R R l V
E E E E E C E E E N C E E E N E E E E e C
S S S S S C S S S D C S S S D S S S S d C
E E E E E I E E E I E E E E E E E 4 I
R R R R R O R R R N R R R R R R R 1 O
V V V V V V V V T V V V V V V V
E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\keshe\miaobiao.rpt
miaobiao
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 5/16( 31%) 7/ 8( 87%) 0/16( 0%) 4/36( 11%)
B: LC17 - LC32 16/16(100%) 8/ 8(100%) 10/16( 62%) 12/36( 33%)
C: LC33 - LC48 7/16( 43%) 8/ 8(100%) 0/16( 0%) 8/36( 22%)
D: LC49 - LC64 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 16/16(100%) 1/ 8( 12%) 5/16( 31%) 21/36( 58%)
F: LC81 - LC96 16/16(100%) 8/ 8(100%) 13/16( 81%) 18/36( 50%)
G: LC97 - LC112 7/16( 43%) 8/ 8(100%) 0/16( 0%) 8/36( 22%)
H: LC113 - LC128 14/16( 87%) 8/ 8(100%) 8/16( 50%) 13/36( 36%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 48/64 ( 75%)
Total logic cells used: 81/128 ( 63%)
Total shareable expanders used: 23/128 ( 17%)
Total Turbo logic cells used: 81/128 ( 63%)
Total shareable expanders not available (n/a): 13/128 ( 10%)
Average fan-in: 6.23
Total fan-in: 505
Total input pins required: 3
Total fast input logic cells required: 0
Total output pins required: 42
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 81
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