count60.rpt

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Device-Specific Information:                              f:\keshe\count60.rpt
count60

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC23 co
        | +--------------- LC26 count00
        | | +------------- LC17 count01
        | | | +----------- LC19 count02
        | | | | +--------- LC21 count03
        | | | | | +------- LC18 count10
        | | | | | | +----- LC24 count11
        | | | | | | | +--- LC27 count12
        | | | | | | | | +- LC22 count13
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC23 -> * - - - - - - - - | - * | <-- co
LC26 -> * * * * * * * * * | - * | <-- count00
LC17 -> * * * * * * * * * | - * | <-- count01
LC19 -> * * - * * * * * * | - * | <-- count02
LC21 -> * * * * * * * * * | - * | <-- count03
LC18 -> * - - - - * * * - | - * | <-- count10
LC24 -> * - - - - * * * - | - * | <-- count11
LC27 -> * - - - - * * * - | - * | <-- count12
LC22 -> * - - - - * * * * | - * | <-- count13

Pin
43   -> - - - - - - - - - | - - | <-- clk
5    -> * * * * * * * * * | - * | <-- jn
4    -> - * * * * * * * * | - * | <-- rd


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              f:\keshe\count60.rpt
count60

** EQUATIONS **

clk      : INPUT;
jn       : INPUT;
rd       : INPUT;

-- Node name is 'co' = ':12' 
-- Equation name is 'co', type is output 
 co      = DFFE( _EQ001 $  GND, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !count00 & !count01 & !count02 &  count03 &  count10 & !count11 & 
              count12 & !count13 &  jn
         #  co & !count00 & !count01 & !count02
         #  co & !count10 & !count11 & !count13
         #  co & !count12 & !count13
         #  co &  _X001;
  _X001  = EXP( count03 &  jn);

-- Node name is 'count00' = 'cnt00' 
-- Equation name is 'count00', location is LC026, type is output.
 count00 = DFFE( _EQ002 $ !jn, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ002 = !count00 & !count01 & !count02 &  jn
         # !count00 & !count03 &  jn
         # !count00 & !jn;

-- Node name is 'count01' = 'cnt01' 
-- Equation name is 'count01', location is LC017, type is output.
 count01 = TFFE( _EQ003, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ003 =  count00 & !count01 & !count03 &  jn
         #  count00 &  count01 &  jn
         #  count01 &  count03 &  jn;

-- Node name is 'count02' = 'cnt02' 
-- Equation name is 'count02', location is LC019, type is output.
 count02 = TFFE( _EQ004, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ004 =  count00 &  count01 & !count02 & !count03 &  jn
         #  count00 &  count01 &  count02 &  jn
         #  count02 &  count03 &  jn;

-- Node name is 'count03' = 'cnt03' 
-- Equation name is 'count03', location is LC021, type is output.
 count03 = TFFE(!_EQ005, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ005 = !count00 & !count01 & !count02 &  count03 &  _X002
         # !count03 &  _X002
         # !jn;
  _X002  = EXP( count00 &  count01 &  count02);

-- Node name is 'count10' = 'cnt10' 
-- Equation name is 'count10', location is LC018, type is output.
 count10 = TFFE(!_EQ006, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ006 = !count10 &  count11 &  count12
         # !count00 & !count01 & !count02
         # !count10 &  count13
         #  _X001;
  _X001  = EXP( count03 &  jn);

-- Node name is 'count11' = 'cnt11' 
-- Equation name is 'count11', location is LC024, type is output.
 count11 = TFFE( _EQ007, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ007 =  count03 &  count10 & !count11 & !count12 & !count13 &  jn & 
              _X003
         #  count03 &  count10 &  count11 &  jn &  _X003
         #  count03 &  count11 &  count12 &  jn &  _X003
         #  count03 &  count11 &  count13 &  jn &  _X003;
  _X003  = EXP(!count00 & !count01 & !count02);

-- Node name is 'count12' = 'cnt12' 
-- Equation name is 'count12', location is LC027, type is output.
 count12 = TFFE( _EQ008, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ008 =  count03 &  count10 &  count11 & !count12 & !count13 &  jn & 
              _X003
         #  count00 &  count03 &  count12 &  jn &  _X004
         #  count01 &  count03 &  count12 &  jn &  _X004
         #  count02 &  count03 &  count12 &  jn &  _X004;
  _X003  = EXP(!count00 & !count01 & !count02);
  _X004  = EXP(!count10 & !count11 & !count13);

-- Node name is 'count13' = 'cnt13' 
-- Equation name is 'count13', location is LC022, type is output.
 count13 = TFFE( _EQ009, GLOBAL( clk), !rd,  VCC,  VCC);
  _EQ009 =  count03 &  count13 &  jn &  _X003;
  _X003  = EXP(!count00 & !count01 & !count02);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                       f:\keshe\count60.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,276K