decl7s.vhd

基于FPGS的数字秒表设计文件 含有计时

library ieee;
use ieee.std_logic_1164.all;
entity decl7s is
port(a:in std_logic_vector(3 downto 0);
led7s:out std_logic_vector(6 downto 0));
end;
architecture one of decl7s is
begin
process(a)
begin
case a is
when"0000"=>led7s<="0111111";
when"0001"=>led7s<="0000110";
when"0010"=>led7s<="1011011";
when"0011"=>led7s<="1001111";
when"0100"=>led7s<="1100110";
when"0101"=>led7s<="1101101";
when"0110"=>led7s<="1111101";
when"0111"=>led7s<="0000111";
when"1000"=>led7s<="1111111";
when"1001"=>led7s<="1101111";
when"1010"=>led7s<="1110111";
when"1011"=>led7s<="1111100";
when"1100"=>led7s<="0111001";
when"1101"=>led7s<="1011110";
when"1110"=>led7s<="1111001";
when"1111"=>led7s<="1110001";
when others=>null;
end case;
end process;
end;