prev_cmp_ccd_driver.qmsg

verilog HDL语言

{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 01 21:23:34 2008 " "Info: Processing ended: Tue Jul 01 21:23:34 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 01 21:23:44 2008 " "Info: Processing started: Tue Jul 01 21:23:44 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off CCD_DRIVER -c ccd_dr " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off CCD_DRIVER -c ccd_dr" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "123 " "Info: Allocated 123 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 01 21:23:48 2008 " "Info: Processing ended: Tue Jul 01 21:23:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 01 21:23:53 2008 " "Info: Processing started: Tue Jul 01 21:23:53 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off CCD_DRIVER -c ccd_dr " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CCD_DRIVER -c ccd_dr" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 18 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt1\[5\]~reg0 register ccd_sh~reg0 151.52 MHz 6.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 151.52 MHz between source register \"cnt1\[5\]~reg0\" and destination register \"ccd_sh~reg0\" (period= 6.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns + Longest register register " "Info: + Longest register to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt1\[5\]~reg0 1 REG LC3 33 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 33; REG Node = 'cnt1\[5\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt1[5]~reg0 } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 53 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.800 ns) 3.100 ns Selector4~111 2 COMB SEXP38 1 " "Info: 2: + IC(1.300 ns) + CELL(1.800 ns) = 3.100 ns; Loc. = SEXP38; Fanout = 1; COMB Node = 'Selector4~111'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { cnt1[5]~reg0 Selector4~111 } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 4.600 ns ccd_sh~reg0 3 REG LC36 4 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 4.600 ns; Loc. = LC36; Fanout = 4; REG Node = 'ccd_sh~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { Selector4~111 ccd_sh~reg0 } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 86 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns ( 71.74 % ) " "Info: Total cell delay = 3.300 ns ( 71.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 28.26 % ) " "Info: Total interconnect delay = 1.300 ns ( 28.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { cnt1[5]~reg0 Selector4~111 ccd_sh~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.600 ns" { cnt1[5]~reg0 {} Selector4~111 {} ccd_sh~reg0 {} } { 0.000ns 1.300ns 0.000ns } { 0.000ns 1.800ns 1.500ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.600 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns clk 1 CLK PIN_43 27 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 27; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.600 ns ccd_sh~reg0 2 REG LC36 4 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC36; Fanout = 4; REG Node = 'ccd_sh~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk ccd_sh~reg0 } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 86 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk ccd_sh~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk {} clk~out {} ccd_sh~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.600 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns clk 1 CLK PIN_43 27 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 27; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.600 ns cnt1\[5\]~reg0 2 REG LC3 33 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC3; Fanout = 33; REG Node = 'cnt1\[5\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk cnt1[5]~reg0 } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 53 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk cnt1[5]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk {} clk~out {} cnt1[5]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk ccd_sh~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk {} clk~out {} ccd_sh~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk cnt1[5]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk {} clk~out {} cnt1[5]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 53 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 86 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { cnt1[5]~reg0 Selector4~111 ccd_sh~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.600 ns" { cnt1[5]~reg0 {} Selector4~111 {} ccd_sh~reg0 {} } { 0.000ns 1.300ns 0.000ns } { 0.000ns 1.800ns 1.500ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk ccd_sh~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk {} clk~out {} ccd_sh~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk cnt1[5]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk {} clk~out {} cnt1[5]~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk ccd_cp ccd_sh~reg0 6.300 ns register " "Info: tco from clock \"clk\" to destination pin \"ccd_cp\" through register \"ccd_sh~reg0\" is 6.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.600 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 1.000 ns clk 1 CLK PIN_43 27 " "Info: 1: + IC(0.000 ns) + CELL(1.000 ns) = 1.000 ns; Loc. = PIN_43; Fanout = 27; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 1.600 ns ccd_sh~reg0 2 REG LC36 4 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 1.600 ns; Loc. = LC36; Fanout = 4; REG Node = 'ccd_sh~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk ccd_sh~reg0 } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 86 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 100.00 % ) " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk ccd_sh~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk {} clk~out {} ccd_sh~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 86 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ccd_sh~reg0 1 REG LC36 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 4; REG Node = 'ccd_sh~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ccd_sh~reg0 } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 86 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.100 ns) 3.200 ns ccd_cp~9 2 COMB LC17 1 " "Info: 2: + IC(1.100 ns) + CELL(2.100 ns) = 3.200 ns; Loc. = LC17; Fanout = 1; COMB Node = 'ccd_cp~9'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { ccd_sh~reg0 ccd_cp~9 } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 4.000 ns ccd_cp 3 PIN PIN_21 0 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 4.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'ccd_cp'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { ccd_cp~9 ccd_cp } "NODE_NAME" } } { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 72.50 % ) " "Info: Total cell delay = 2.900 ns ( 72.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns ( 27.50 % ) " "Info: Total interconnect delay = 1.100 ns ( 27.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { ccd_sh~reg0 ccd_cp~9 ccd_cp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.000 ns" { ccd_sh~reg0 {} ccd_cp~9 {} ccd_cp {} } { 0.000ns 1.100ns 0.000ns } { 0.000ns 2.100ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { clk ccd_sh~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.600 ns" { clk {} clk~out {} ccd_sh~reg0 {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.000ns 0.600ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { ccd_sh~reg0 ccd_cp~9 ccd_cp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.000 ns" { ccd_sh~reg0 {} ccd_cp~9 {} ccd_cp {} } { 0.000ns 1.100ns 0.000ns } { 0.000ns 2.100ns 0.800ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 01 21:23:56 2008 " "Info: Processing ended: Tue Jul 01 21:23:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2 s " "Info: Quartus II Full Compilation was successful. 0 errors, 2 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}