ccd_dr.v

verilog HDL语言

module ccd_dr(//for test;
cnt1, cnt2,
//for test;
clk, ccd_clk1, ccd_clk2, ccd_sh, ccd_rs, ccd_cp, ccd_en, ccd_clk);
 
  parameter p_a = 12'd2099;  //all driver clock numbers
  parameter p_u = 12'd2048;  // useful pixel numbers
  parameter p_n = 6'd36;    //noused pixel numbers
  parameter clk_in = 50;    //clk_in is the clk input frequency Mhz
  parameter os_out = 1;      //os_out is the output driver frequency Mhz
  parameter cnt1_num = 8'd49;//(clk_in / os_out) - 1;  //counter1 is used to low down the input clk frequency,cnt1_num is the number to count
  parameter clk1_con = 8'd24;//((clk_in / os_out) / 2) - 1;    //the position to converse the output clk1  
  parameter rs_sta = 8'd34;//(68 / 100) * (clk_in / os_out);   //use even to get integer
  parameter rs_end = 8'd39;//(78 / 100) * (clk_in / os_out); //use even to get integer
  parameter cp_sta = 8'd40;//(80 / 100) * (clk_in / os_out);   //use even to get integer
  parameter cp_end = 8'd45;//(90 / 100) * (clk_in / os_out);  //use even to get integer
 
  input clk;
  output ccd_clk1;
  output ccd_clk2;
  output ccd_sh;
  output ccd_rs;
  output ccd_cp;
  output ccd_en;
  output ccd_clk;
  //for test begin;
  output [7:0] cnt1;
  output [11:0] cnt2;
  //for test end;

 
  reg ccd_clk1;  //driver
  wire ccd_clk2;  //driver
  reg ccd_sh;    //driver
  wire ccd_cp;  //driver
  wire ccd_rs;  //driver
  reg ccd_en;    //1 means usefully pixel.0 means dummy pixel
  reg ccd_clk;   //signal clk;
  reg clk1 = 1;
  reg cp = 1;
  reg rs = 1;   //interal signals;
 // wire clk2;   //clk2 only the RP of clk1;
  reg [7:0] cnt1 = 0;  //1 for period inside counter ,2 for period counter;
  reg [11:0] cnt2 = 0; //1 is 0~199, 2 is 0~2099 for pixels;

//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////            
assign ccd_clk2 = ~ccd_clk1;    //ccd_clk2 only the RP of ccd_clk1;


//counters module begin;
//always_0 begin;             
always @ (posedge clk)
  if(cnt1 == cnt1_num)
    begin
      cnt1 <= 8'd0;
      if(cnt2 == p_a) cnt2 <= 12'd0;
      else cnt2 <= cnt2 + 12'd1;
    end

  else cnt1 <= cnt1 + 8'd1;
//always_0 end;  


//internal signals module begin;
//always_2 begin;
always @ (posedge clk)
 case (cnt1)
  clk1_con - 1 : clk1 <= ~clk1; //clk turning; pre 1 clk for the delay;
  cnt1_num - 1 : clk1 <= ~clk1; //clk turning; pre 1 clk for the delay;
  rs_sta : rs <= 0;     //set rs; pre 1 clk for the delay;
  rs_end : rs <= 1;     //reset rs; pre 1 clk for the delay;
  cp_sta : cp <= 0;       //set cp; pre 1 clk for the delay;
  cp_end : cp <= 1;     //reset cp; pre 1 clk for the delay;
 
 endcase  
//internal signals module end;
//always_2 end;


//always_3 begin;
always @ (posedge clk)
  if(cnt1 == 8'd15) ccd_clk <= ~ccd_clk;
  else if(cnt1 == 8'd40) ccd_clk <= ~ccd_clk;
 
always @ (posedge clk)
if(cnt1 <= (cnt1_num - 10))
  begin
    if(cnt2 >= (31 + 3) && cnt2 <= (31 + 3 + p_u))
      ccd_en <= 1;
    else ccd_en <= 0;
    case(cnt2)
      12'd0 : begin
          ccd_clk1 <= 1;
          if(cnt1 <= (clk1_con - 1))
            ccd_sh <= 0;
          else ccd_sh <= 1;
          end
      12'd1 : begin
          ccd_clk1 <= 1;
          ccd_sh <= 1;
          end
      12'd2 : begin
          ccd_clk1 <= 1;
          ccd_sh <= 0;
          end
      12'd3 : begin
          ccd_sh <= 0;
          if(cnt1 < 24) ccd_clk1 <= 1;
          else ccd_clk1 <= clk1;
          end
      default : ccd_clk1 <= clk1;
    endcase
  end
assign ccd_rs = rs && ~ccd_sh;
assign ccd_cp = cp && ~ccd_sh;
//always_3 end;
//the old    


endmodule