ccd_dr.tan.summary

verilog HDL语言

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.300 ns
From           : ccd_sh~reg0
To             : ccd_rs
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 151.52 MHz ( period = 6.600 ns )
From           : cnt1[4]~reg0
To             : ccd_clk1~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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