stdout.log

来自「自己实用Verilog编写的UART程序」· LOG 代码 · 共 25 行

License checkout: synplify_pc

Starting:    e:\Libero\Synplify\Synplify_862H\bin\mbin\synplify.exe
Install:     e:\Libero\Synplify\Synplify_862H
Date:        Wed Mar 26 15:01:21 2008
Version:     8.6.2H


Arguments:   uart_test_syn.prj
ProductType: synplify

License: synplify_pc node-locked 



At line 1 while processing "E:\所有其他\安装文件\FPGA\actel\实验例程\UART\synthesis\uart_test_syn.prj"
couldn't read file "E:\所有其他\安装文件\FPGA\actel\实验例程\UART\synthesis\uart_test_syn.prj": no such file or directory


Error: Project load failed.

exit status=0