uart_test.tlg

自己实用Verilog编写的UART程序

Selecting top level module uart_test
@N: CG364 :"C:\Actelprj\ProASIC3\UART\hdl\rec.v":5:7:5:9|Synthesizing module rec

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\rec.v":37:0:37:5|Pruning bit <9> of UartBuff_6[9:0] - not in use ...

@N: CG364 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":6:7:6:10|Synthesizing module send

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":54:0:54:5|Pruning bit <9> of Datainbuf2_6[9:0] - not in use ...

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":54:0:54:5|Pruning bit <8> of Datainbuf2_6[9:0] - not in use ...

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":54:0:54:5|Pruning bit <7> of Datainbuf2_6[9:0] - not in use ...

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":54:0:54:5|Pruning bit <6> of Datainbuf2_6[9:0] - not in use ...

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":54:0:54:5|Pruning bit <5> of Datainbuf2_6[9:0] - not in use ...

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":54:0:54:5|Pruning bit <4> of Datainbuf2_6[9:0] - not in use ...

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":54:0:54:5|Pruning bit <3> of Datainbuf2_6[9:0] - not in use ...

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":54:0:54:5|Pruning bit <2> of Datainbuf2_6[9:0] - not in use ...

@W: CL170 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":54:0:54:5|Pruning bit <1> of Datainbuf2_6[9:0] - not in use ...

@W: CL189 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":42:0:42:5|Register bit Datainbuf[0] is always 0, optimizing ...
@W: CL189 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":42:0:42:5|Register bit Datainbuf[9] is always 1, optimizing ...
@W: CL171 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":42:0:42:5|Pruning Register bit <9> of Datainbuf[9:0] 

@W: CL171 :"C:\Actelprj\ProASIC3\UART\hdl\send.v":42:0:42:5|Pruning Register bit <0> of Datainbuf[9:0] 

@N: CG364 :"C:\Actelprj\ProASIC3\UART\hdl\uart_test.v":5:7:5:15|Synthesizing module uart_test